SY10H843 Search Results

SY10H843 Datasheets (1)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
SY10H843ZC		Synergy Semiconductor	SINGLE SUPPLY PECL-TTL 1:4 CLOCK DRIVER		Scan	PDF

SY10H843 Datasheets Context Search

Catalog Datasheet	MFG & Type	PDF	Document Tags
74FCT244D Abstract: SY100E111 SY10E111 SY10H641 SY10H841 SY10H842 50 ohm micro stripline Text: CLOCK SYSTEM DESIGN Differential PECL signals, such as those used by the SY10E111 and SY10H842, have unique advantages for clock distribution systems. Differential PECL signals provide good noise rejection. Because they are differential and have low swing, they minimize EM radiation from	Original	PDF	SY10E111 SY10H842, AN-01 74FCT244D SY100E111 SY10H641 SY10H841 SY10H842 50 ohm micro stripline
Untitled Abstract: No abstract text available Text: SINGLE_SUPPLY PECL-TTL 1:4 CLOCK DRIVER SYNERGY p rE f LIM m m IN IIIII rv PR AR Y SY1Q 1D0H843 SEM IC O N D U C TO R DESCRIPTION FEATURES • Translates positive ECL to TTL PECL-TTL ■ 300ps pln-to-pin skew ■ Guaranteed skew spec ■ Differential internal design for Increased noise	OCR Scan	PDF	1D0H843 300ps SY10H843 SY100H843 SY10/100H843 SY10H843ZC SY100H843ZC Z16-1
SD013 Abstract: SY10H843ZC Text: SINGLE SUPPLY PECL-TTL 1:4 CLOCK DRIVER Clockworks PRELIMINARY SY10/100H843 DESCRIPTION FEATURES Translates positive ECL to TTL PECL-TTL 300ps pin-to-pin skew Guaranteed skew spec Differential internal design for increased noise immunity and stable threshold inputs	OCR Scan	PDF	SY10/100H843 300ps SY10H843 SY100H843 40MHz 50MHz SD013Ã 000101G SY10H843ZC SD013
Untitled Abstract: No abstract text available Text: ^ e v u m r v S IN G L E s S S S Ê Ê S F S U P P L Y 1:4C L0C K D R IV ER p r e l i m i n a r y svittiooH 843 DESCRIPTION FEATURES • Translates positive ECL to TTL PECL-TTL ■ 300ps pln-to-pin skew ■ Guaranteed skew spec ■ Differential internal design for increased noise	OCR Scan	PDF	300ps SY10H843 SY100H843 SY10/100H843 SY10H843ZC Z16-1 SY100H843ZC
Untitled Abstract: No abstract text available Text: * SYNERGY CLO CK SYSTEM DESIGN APPLICATIONS N O T E A N - 02 S E M IC O N D U C T O R INTRODUCTION C lock d istribution is a sig n ifica n t design challenge for system s operating above 25M H z. The S ynergy PECL series of clock chips sim p lifie s designs by sig n ifica n tly	OCR Scan	PDF	subsyst37
Untitled Abstract: No abstract text available Text: « SYNERGY SEMICONDUCTOR S IN G L E S U P P L Y P E C L -T T L ClockW orks1M 1 : 4 C L O C K D R IV E R SvTo/lo'oHsla DESCRIPTION FEATURES • Translates positive ECL to TTL PECL-TTL ■ 300ps pin-to-pin skew ■ Guaranteed skew spec ■ Differential internal design for increased noise	OCR Scan	PDF	300ps SY10H843 SY100H843 TDD13Ã SY10/100H843 SY10H843ZC Z16-1 SY100H843ZC 1DD13Ã