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    SN74ALVC3 Search Results

    SN74ALVC3 Result Highlights (5)

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    SN74ALVC32PW Texas Instruments Quadruple 2-Input Positive-OR Gate 14-TSSOP -40 to 85 Visit Texas Instruments Buy
    SN74ALVC32DGVR Texas Instruments Quadruple 2-Input Positive-OR Gate 14-TVSOP -40 to 85 Visit Texas Instruments Buy
    SN74ALVC32PWE4 Texas Instruments Quadruple 2-Input Positive-OR Gate 14-TSSOP -40 to 85 Visit Texas Instruments Buy
    SN74ALVC32NSR Texas Instruments Quadruple 2-Input Positive-OR Gate 14-SO -40 to 85 Visit Texas Instruments Buy
    SN74ALVC32D Texas Instruments Quadruple 2-Input Positive-OR Gate 14-SOIC -40 to 85 Visit Texas Instruments Buy
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    SN74ALVC3 Price and Stock

    Texas Instruments SN74ALVC32PWR

    IC GATE OR 4CH 2-INP 14TSSOP
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    Texas Instruments SN74ALVC32DR

    IC GATE OR 4CH 2-INP 14SOIC
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    Quest Components SN74ALVC32DR 675
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    Component Electronics, Inc SN74ALVC32DR 2,480
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    Texas Instruments SN74ALVC32DGVR

    IC GATE OR 4CH 2-INP 14TVSOP
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    DigiKey SN74ALVC32DGVR Cut Tape 3,956 1
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    SN74ALVC32DGVR Digi-Reel 3,956 1
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    SN74ALVC32DGVR Reel 2,000 2,000
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    Quest Components SN74ALVC32DGVR 46
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    New Advantage Corporation SN74ALVC32DGVR 1,436 1
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    Texas Instruments SN74ALVC32NSR

    IC GATE OR 4CH 2-INP 14SO
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    Texas Instruments SN74ALVC32D

    IC GATE OR 4CH 2-INP 14SOIC
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    DigiKey SN74ALVC32D Tube 1,728 1
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    SN74ALVC32D 1,311 795
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    SN74ALVC32D 1,250 795
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    SN74ALVC32D 1,018 795
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    Quest Components SN74ALVC32D 178
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    SN74ALVC3 Datasheets (139)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    SN74ALVC32 Texas Instruments Quadruple 2-Input Positive-OR Gate Original PDF
    SN74ALVC32D Texas Instruments SN74ALVC32 - Quadruple 2-Input Positive-OR Gate 14-SOIC -40 to 85 Original PDF
    SN74ALVC32D Texas Instruments QUADRUPLE 2-INPUT POSITIVE-OR GATE Original PDF
    SN74ALVC32D Texas Instruments Quadruple 2-Input Positive-OR Gate 14-SOIC -40 to 85 Original PDF
    SN74ALVC32D Texas Instruments Quadruple 2-Input Positive-OR Gate Original PDF
    SN74ALVC32DE4 Texas Instruments SN74ALVC32 - Quadruple 2-Input Positive-OR Gate 14-SOIC -40 to 85 Original PDF
    SN74ALVC32DE4 Texas Instruments Quadruple 2-Input Positive-OR Gate 14-SOIC -40 to 85 Original PDF
    SN74ALVC32DE4 Texas Instruments Quadruple 2-Input Positive-OR Gate Original PDF
    SN74ALVC32DG4 Texas Instruments SN74ALVC32 - Quadruple 2-Input Positive-OR Gate 14-SOIC -40 to 85 Original PDF
    SN74ALVC32DG4 Texas Instruments Quadruple 2-Input Positive-OR Gate 14-SOIC -40 to 85 Original PDF
    SN74ALVC32DGV Texas Instruments QUADRUPLE 2-INPUT POSITIVE-OR GATE Original PDF
    SN74ALVC32DGV Texas Instruments Quadruple 2-Input Positive-OR Gate Original PDF
    SN74ALVC32DGVR Texas Instruments SN74ALVC32 - Quadruple 2-Input Positive-OR Gate 14-TVSOP -40 to 85 Original PDF
    SN74ALVC32DGVR Texas Instruments Quadruple 2-Input Positive-OR Gate 14-TVSOP -40 to 85 Original PDF
    SN74ALVC32DGVR Texas Instruments Quadruple 2-Input Positive-OR Gate Original PDF
    SN74ALVC32DGVRE4 Texas Instruments Quadruple 2-Input Positive-OR Gate Original PDF
    SN74ALVC32DGVRE4 Texas Instruments SN74ALVC32 - Quadruple 2-Input Positive-OR Gate 14-TVSOP -40 to 85 Original PDF
    SN74ALVC32DGVRE4 Texas Instruments Quadruple 2-Input Positive-OR Gate 14-TVSOP -40 to 85 Original PDF
    SN74ALVC32DGVRG4 Texas Instruments Quadruple 2-Input Positive-OR Gate 14-TVSOP -40 to 85 Original PDF
    SN74ALVC32DGVRG4 Texas Instruments SN74ALVC32 - Quadruple 2-Input Positive-OR Gate 14-TVSOP -40 to 85 Original PDF
    ...

    SN74ALVC3 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    va32

    Abstract: A115-A C101 SN74ALVC32 SN74ALVC32D
    Text: SN74ALVC32 QUADRUPLE 2ĆINPUT POSITIVEĆOR GATE SCES108F − JULY 1997 − REVISED AUGUST 2003 D D D D D D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 2.8 ns at 3.3 V ±24-mA Output Drive at 3.3 V Latch-Up Performance Exceeds 250 mA Per


    Original     		PDF SN74ALVC32 SCES108F 24-mA 000-V A114-A) A115-A) SN74ALVC32 va32 A115-A C101 SN74ALVC32D

    SN74ACT3631

    Abstract: SN74ACT3641 SN74ACT3651 SN74ALVC3631 SN74ALVC3641 SN74ALVC3651
    Text: SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 512 x 36, 1024 × 36, 2048 × 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SDMS025B – OCTOBER 1999 – REVISED JUNE 2000 D D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Clocked FIFO Buffering Data From Port A


    Original     		PDF SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 SDMS025B SN74ACT3631 SN74ACT3641 SN74ACT3651 SN74ALVC3631 SN74ALVC3641 SN74ALVC3651

    A115-A

    Abstract: C101 SN74ALVC32 SN74ALVC32D
    Text: SN74ALVC32 QUADRUPLE 2-INPUT POSITIVE-OR GATE www.ti.com SCES108G – JULY 1997 – REVISED NOVEMBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 2.8 ns at 3.3 V ±24-mA Output Drive at 3.3 V


    Original     		PDF SN74ALVC32 SCES108G 24-mA 000-V A114-A) A115-A) SN74ALVC32 A115-A C101 SN74ALVC32D

    A115-A

    Abstract: C101 SN74ALVC32 SN74ALVC32D VA32
    Text: SN74ALVC32 QUADRUPLE 2-INPUT POSITIVE-OR GATE www.ti.com SCES108G – JULY 1997 – REVISED NOVEMBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 2.8 ns at 3.3 V ±24-mA Output Drive at 3.3 V


    Original     		PDF SN74ALVC32 SCES108G 24-mA 000-V A114-A) A115-A) SN74ALVC32 A115-A C101 SN74ALVC32D VA32

    Untitled

    Abstract: No abstract text available
    Text: Contents Page ALVC Gates/Octals SN74ALVC00 SN74ALVC04 SN74ALVC08 SN74ALVC10 SN74ALVC14 SN74ALVC32 SN74ALVC74 SN74ALVC125 SN74ALVC126 SN74ALVC244 SN74ALVCH244 SN74ALVC245 SN74ALVCH245 SN74ALVCH373 SN74ALVCH374 2–2 Quadruple 2-Input Positive-NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


    Original     		PDF SN74ALVC00 SN74ALVC04 SN74ALVC08 SN74ALVC10 SN74ALVC14 SN74ALVC32 SN74ALVC74 SN74ALVC125 SN74ALVC126 SN74ALVC244

    Untitled

    Abstract: No abstract text available
    Text: SN74ALVC32 QUADRUPLE 2-INPUT POSITIVE-OR GATE SCES108D – JULY 1997 – REVISED AUGUST 1998 D EPIC Enhanced-Performance Implanted D D D D, DGV, OR PW PACKAGE (TOP VIEW CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V


    Original     		PDF SN74ALVC32 SCES108D MIL-STD-883,

    VA32

    Abstract: No abstract text available
    Text: SN74ALVC32 QUADRUPLE 2-INPUT POSITIVE-OR GATE www.ti.com SCES108G – JULY 1997 – REVISED NOVEMBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 2.8 ns at 3.3 V ±24-mA Output Drive at 3.3 V


    Original     		PDF SN74ALVC32 SCES108G 24-mA 000-V A114-A) A115-A) VA32

    SN74ACT3631

    Abstract: SN74ACT3641 SN74ACT3651 SN74ALVC3631 SN74ALVC3641 SN74ALVC3651
    Text: SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 512 x 36, 1024 × 36, 2048 × 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SDMS025B – OCTOBER 1999 – REVISED JUNE 2000 D D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Clocked FIFO Buffering Data From Port A


    Original     		PDF SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 SDMS025B SN74ACT3631 SN74ACT3641 SN74ACT3651 SN74ALVC3631 SN74ALVC3641 SN74ALVC3651

    Untitled

    Abstract: No abstract text available
    Text: SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 512 x 36, 1024 × 36, 2048 × 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SDMS025B – OCTOBER 1999 – REVISED JUNE 2000 D D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Clocked FIFO Buffering Data From Port A


    Original     		PDF SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 SDMS025B SN74ACT3631, SN74ACT3641,

    Untitled

    Abstract: No abstract text available
    Text: SN74ALVC32 QUADRUPLE 2-INPUT POSITIVE-OR GATE www.ti.com SCES108G – JULY 1997 – REVISED NOVEMBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 2.8 ns at 3.3 V ±24-mA Output Drive at 3.3 V


    Original     		PDF SN74ALVC32 SCES108G 24-mA 000-V A114-A) A115-A) SN74ALVC32 scem245

    Untitled

    Abstract: No abstract text available
    Text: SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 512 x 36, 1024 × 36, 2048 × 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SDMS025B – OCTOBER 1999 – REVISED JUNE 2000 D D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Clocked FIFO Buffering Data From Port A


    Original     		PDF SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 SDMS025B SN74ACT3631, SN74ACT3641,

    Untitled

    Abstract: No abstract text available
    Text: SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 512 x 36, 1024 × 36, 2048 × 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SDMS025B – OCTOBER 1999 – REVISED JUNE 2000 D D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Clocked FIFO Buffering Data From Port A


    Original     		PDF SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 SDMS025B SN74ACT3631, SN74ACT3641,

    Untitled

    Abstract: No abstract text available
    Text: SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 512 x 36, 1024 × 36, 2048 × 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SDMS025B – OCTOBER 1999 – REVISED JUNE 2000 D D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Clocked FIFO Buffering Data From Port A


    Original     		PDF SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 SDMS025B

    apr 8910

    Abstract: No abstract text available
    Text: SN74ALVC32 QUADRUPLE 2-INPUT POSITIVE-OR GATE SCES108E – JULY 1997 – REVISED MARCH 2000 D D D D EPIC  Enhanced-Performance Implanted CMOS Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)


    Original     		PDF SN74ALVC32 SCES108E MIL-STD-883, SN74ALVC32PWR SN74ALVC32 SCEM245, apr 8910

    va32

    Abstract: No abstract text available
    Text: SN74ALVC32 QUADRUPLE 2-INPUT POSITIVE-OR GATE www.ti.com SCES108G – JULY 1997 – REVISED NOVEMBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 2.8 ns at 3.3 V ±24-mA Output Drive at 3.3 V


    Original     		PDF SN74ALVC32 SCES108G 24-mA 000-V A114-A) A115-A) MTSS001C 4040064/F va32

    ALVC32

    Abstract: No abstract text available
    Text: SN74ALVC32 QUADRUPLE 2-INPUT POSITIVE-OR GATE www.ti.com SCES108G – JULY 1997 – REVISED NOVEMBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 2.8 ns at 3.3 V ±24-mA Output Drive at 3.3 V


    Original     		PDF SN74ALVC32 SCES108G 24-mA 000-V A114-A) A115-A) SN74ALVti ALVC32

    Untitled

    Abstract: No abstract text available
    Text: SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 512 x 36, 1024 × 36, 2048 × 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SDMS025B – OCTOBER 1999 – REVISED JUNE 2000 D D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Clocked FIFO Buffering Data From Port A


    Original     		PDF SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 SDMS025B SN74ACT3631, SN74ACT3641,

    Untitled

    Abstract: No abstract text available
    Text: SN74ALVC32 QUADRUPLE 2-INPUT POSITIVE-OR GATE www.ti.com SCES108G – JULY 1997 – REVISED NOVEMBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 2.8 ns at 3.3 V ±24-mA Output Drive at 3.3 V


    Original     		PDF SN74ALVC32 SCES108G 24-mA 000-V A114-A) A115-A) SN74ALVC3

    Untitled

    Abstract: No abstract text available
    Text: SN74ALVC32 QUADRUPLE 2-INPUT POSITIVE-OR GATE www.ti.com SCES108G – JULY 1997 – REVISED NOVEMBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 2.8 ns at 3.3 V ±24-mA Output Drive at 3.3 V


    Original     		PDF SN74ALVC32 SCES108G 24-mA 000-V A114-A) A115-A)

    MO-194

    Abstract: MPDS006C SN74ALVC32
    Text: SN74ALVC32 QUADRUPLE 2-INPUT POSITIVE-OR GATE SCES108E – JULY 1997 – REVISED MARCH 2000 D D D D EPIC  Enhanced-Performance Implanted CMOS Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)


    Original     		PDF SN74ALVC32 SCES108E MIL-STD-883, MO-194 MPDS006C SN74ALVC32

    A115-A

    Abstract: C101 SN74ALVC32 SN74ALVC32D
    Text: SN74ALVC32 QUADRUPLE 2-INPUT POSITIVE-OR GATE www.ti.com SCES108G – JULY 1997 – REVISED NOVEMBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 2.8 ns at 3.3 V ±24-mA Output Drive at 3.3 V


    Original     		PDF SN74ALVC32 SCES108G 24-mA 000-V A114-A) A115-A) SN74ALVC32 A115-A C101 SN74ALVC32D

    SN74ALVC32

    Abstract: No abstract text available
    Text: SN74ALVC32 QUADRUPLE 2-INPUT POSITIVE-OR GATE SCES108E – JULY 1997 – REVISED MARCH 2000 D D D D EPIC  Enhanced-Performance Implanted CMOS Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)


    Original     		PDF SN74ALVC32 SCES108E MIL-STD-883, SN74ALVC32

    Untitled

    Abstract: No abstract text available
    Text: SN74ALVC32 QUADRUPLE 2-INPUT POSITIVE-OR GATE www.ti.com SCES108G – JULY 1997 – REVISED NOVEMBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 2.8 ns at 3.3 V ±24-mA Output Drive at 3.3 V


    Original     		PDF SN74ALVC32 SCES108G 24-mA 000-V A114-A) A115-A) MTSS001C 4040064/F

    Untitled

    Abstract: No abstract text available
    Text: SN74ALVC32 QUADRUPLE 2-INPUT POSITIVE-OR GATE SCES108D - JULY 1997 - REVISED AUGUST 1998 • EPIC Enhanced-Performance Implanted CMOS Submicron Process • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)


    OCR Scan     		PDF SN74ALVC32 SCES108D MIL-STD-883, JESD17