Untitled
Abstract: No abstract text available
Text: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE SCAS284K – JANUARY 1993 – REVISED SEPTEMBER 2002 D 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3C 3B 3A 3Y RGY PACKAGE TOP VIEW description/ordering information This triple 3-input positive-NAND gate is designed
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Original
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SN74LVC10A
SCAS284K
000-V
A114-A)
A115-A)
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Untitled
Abstract: No abstract text available
Text: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCAS284O – JANUARY 1993 – REVISED JULY 2005 FEATURES • 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3C 3B 3A 3Y RGY PACKAGE TOP VIEW 1B 2A 2B 2C 2Y VCC • 1 1 14 13 1C 12 1Y 2 3 4 11 3C 5 6 10 3B
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SN74LVC10A
SCAS284O
000-V
A114-A)
A115-A)
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Untitled
Abstract: No abstract text available
Text: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCAS284O – JANUARY 1993 – REVISED JULY 2005 FEATURES • 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3C 3B 3A 3Y RGY PACKAGE TOP VIEW 1B 2A 2B 2C 2Y VCC • 1 1 14 13 1C 12 1Y 2 3 4 11 3C 5 6 10 3B
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SN74LVC10A
SCAS284O
000-V
A114-A)
A115-A)
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Untitled
Abstract: No abstract text available
Text: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCAS284O – JANUARY 1993 – REVISED JULY 2005 FEATURES • 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3C 3B 3A 3Y RGY PACKAGE TOP VIEW 1B 2A 2B 2C 2Y VCC • 1 1 14 13 1C 12 1Y 2 3 4 11 3C 5 6 10 3B
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SN74LVC10A
SCAS284O
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SN74LVC10A
Abstract: No abstract text available
Text: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE SCAS284G – JANUARY 1993 – REVISED OCTOBER 1998 D D D D D D D EPIC Enhanced-Performance Implanted CMOS Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
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SN74LVC10A
SCAS284G
MIL-STD-883,
SN74LVC10A
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Untitled
Abstract: No abstract text available
Text: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE SCAS284J – JANUARY 1993 – REVISED AUGUST 2002 D 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3C 3B 3A 3Y RGY PACKAGE TOP VIEW description/ordering information This triple 3-input positive-NAND gate is designed
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Original
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SN74LVC10A
SCAS284J
000-V
A114-A)
A115-A)
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Untitled
Abstract: No abstract text available
Text: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE SCAS284H – JANUARY 1993 – REVISED MARCH 2002 D D D D D D, DB, NS, OR PW PACKAGE TOP VIEW Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C
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SN74LVC10A
SCAS284H
000-V
A114-A)
A115-A)
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Untitled
Abstract: No abstract text available
Text: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCAS284O – JANUARY 1993 – REVISED JULY 2005 FEATURES • 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3C 3B 3A 3Y RGY PACKAGE TOP VIEW 1B 2A 2B 2C 2Y VCC • 1 1 14 13 1C 12 1Y 2 3 4 11 3C 5 6 10 3B
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SN74LVC10A
SCAS284O
000-V
A114-A)
A115-A)
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Untitled
Abstract: No abstract text available
Text: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE SCAS284I – JANUARY 1993 – REVISED JULY 2002 D D D D D D D D, DB, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 4.9 ns Typical VOLP (Output Ground Bounce)
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SN74LVC10A
SCAS284I
000-V
A114-A)
A115-A)
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Untitled
Abstract: No abstract text available
Text: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCAS284O – JANUARY 1993 – REVISED JULY 2005 FEATURES • 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3C 3B 3A 3Y RGY PACKAGE TOP VIEW 1B 2A 2B 2C 2Y VCC • 1 1 14 13 1C 12 1Y 2 3 4 11 3C 5 6 10 3B
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SN74LVC10A
SCAS284O
000-V
A114-A)
A115-A)
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"NAND Gate"
Abstract: SN74LVC10A SCAS284D
Text: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE SCAS284D – JANUARY 1993 – REVISED JANUARY 1997 D D D D D D D EPIC Enhanced-Performance Implanted CMOS Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
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SN74LVC10A
SCAS284D
MIL-STD-883,
JESD-17
"NAND Gate"
SN74LVC10A
SCAS284D
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Untitled
Abstract: No abstract text available
Text: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCAS284O – JANUARY 1993 – REVISED JULY 2005 FEATURES • 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3C 3B 3A 3Y RGY PACKAGE TOP VIEW 1B 2A 2B 2C 2Y VCC • 1 1 14 13 1C 12 1Y 2 3 4 11 3C 5 6 10 3B
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SN74LVC10A
SCAS284O
000-V
A114-A)
A115-A)
G3157
SNS74LVC2G53
scyb014
scyb005
scym001
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Untitled
Abstract: No abstract text available
Text: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCAS284O – JANUARY 1993 – REVISED JULY 2005 FEATURES • 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3C 3B 3A 3Y RGY PACKAGE TOP VIEW 1B 2A 2B 2C 2Y VCC • 1 1 14 13 1C 12 1Y 2 3 4 11 3C 5 6 10 3B
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SN74LVC10A
SCAS284O
000-V
A114-A)
A115-A)
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A115-A
Abstract: SN74LVC10A SN74LVC10AD SN74LVC10ADR SN74LVC10ARGYR
Text: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCAS284O – JANUARY 1993 – REVISED JULY 2005 FEATURES • 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3C 3B 3A 3Y RGY PACKAGE TOP VIEW 1B 2A 2B 2C 2Y VCC • 1 1 14 13 1C 12 1Y 2 3 4 11 3C 5 6 10 3B
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SN74LVC10A
SCAS284O
A115-A
SN74LVC10A
SN74LVC10AD
SN74LVC10ADR
SN74LVC10ARGYR
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Untitled
Abstract: No abstract text available
Text: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE SCAS284K – JANUARY 1993 – REVISED SEPTEMBER 2002 D 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3C 3B 3A 3Y RGY PACKAGE TOP VIEW description/ordering information This triple 3-input positive-NAND gate is designed
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Original
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SN74LVC10A
SCAS284K
000-V
A114-A)
A115-A)
SN74LVC10ARGYR
SN74LVC10A
SCEM011A,
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A115-A
Abstract: SN74LVC10A SN74LVC10AD SN74LVC10ADR SN74LVC10ARGYR
Text: SN74LVC10A TRIPLE 3ĆINPUT POSITIVEĆNAND GATE SCAS284M − JANUARY 1993 − REVISED JULY 2003 D 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3C 3B 3A 3Y RGY PACKAGE TOP VIEW description/ordering information This triple 3-input positive-NAND gate is designed
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Original
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SN74LVC10A
SCAS284M
SN74LVC10A
A115-A
SN74LVC10AD
SN74LVC10ADR
SN74LVC10ARGYR
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LC10A
Abstract: No abstract text available
Text: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCAS284O – JANUARY 1993 – REVISED JULY 2005 FEATURES • 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3C 3B 3A 3Y RGY PACKAGE TOP VIEW 1B 2A 2B 2C 2Y VCC • 1 1 14 13 1C 12 1Y 2 3 4 11 3C 5 6 10 3B
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SN74LVC10A
SCAS284O
000-V
A114-A)
A115-A)
LC10A
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Untitled
Abstract: No abstract text available
Text: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCAS284O – JANUARY 1993 – REVISED JULY 2005 FEATURES • 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3C 3B 3A 3Y RGY PACKAGE TOP VIEW 1B 2A 2B 2C 2Y VCC • 1 1 14 13 1C 12 1Y 2 3 4 11 3C 5 6 10 3B
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Original
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SN74LVC10A
SCAS284O
000-V
A114-A)
A115-A)
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PDF
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SN74LVC10A
Abstract: No abstract text available
Text: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE SCAS284C – JANUARY 1993 – REVISED SEPTEMBER 1996 D D D D D D D EPIC Enhanced-Performance Implanted CMOS Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
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Original
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SN74LVC10A
SCAS284C
MIL-STD-883,
JESD-17
SN74LVC10A
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PDF
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Untitled
Abstract: No abstract text available
Text: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCAS284O – JANUARY 1993 – REVISED JULY 2005 FEATURES • 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3C 3B 3A 3Y RGY PACKAGE TOP VIEW 1B 2A 2B 2C 2Y VCC • 1 1 14 13 1C 12 1Y 2 3 4 11 3C 5 6 10 3B
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Original
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SN74LVC10A
SCAS284O
000-V
A114-A)
A115-A)
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SN74LVC10
Abstract: A115-A SN74LVC10A SN74LVC10AD SN74LVC10ADR SN74LVC10ARGYR
Text: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCAS284O – JANUARY 1993 – REVISED JULY 2005 FEATURES • 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3C 3B 3A 3Y RGY PACKAGE TOP VIEW 1B 2A 2B 2C 2Y VCC • 1 1 14 13 1C 12 1Y 2 3 4 11 3C 5 6 10 3B
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SN74LVC10A
SCAS284O
SN74LVC10
A115-A
SN74LVC10A
SN74LVC10AD
SN74LVC10ADR
SN74LVC10ARGYR
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2 input nand gate 24v
Abstract: A115-A SN74LVC10A SN74LVC10AD SN74LVC10ADR SN74LVC10ARGYR SN74LVC10
Text: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCAS284N – JANUARY 1993 – REVISED FEBRUARY 2005 FEATURES • 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3C 3B 3A 3Y RGY PACKAGE TOP VIEW 1B 2A 2B 2C 2Y VCC • 1 1 14 13 1C 12 1Y 2 3 4 11 3C 5 6 10 3B
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SN74LVC10A
SCAS284N
2 input nand gate 24v
A115-A
SN74LVC10A
SN74LVC10AD
SN74LVC10ADR
SN74LVC10ARGYR
SN74LVC10
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Untitled
Abstract: No abstract text available
Text: SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE SCAS284E - JANUARY 1993 - REVISED JANUARY 1998 • EPIC Enhanced-Performance Implanted CMOS Submicron Process • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
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OCR Scan
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SN74LVC10A
SCAS284E
MIL-STD-883,
JESD17
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PDF
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Untitled
Abstract: No abstract text available
Text: SN74LVC10 TRIPLE 3-INPUT POSITIVE-NAND GATE SCAS284 - JANUARY 1993 - REVISED MARCH 1994 EPIC Enhanced-Performance Implanted CMOS Submicron Process D, DB, OR PW PACKAGE (TOP VIEW) Typical V q l p (Output Ground Bounce) < 0.8 V at Vc c = 3.3 V, TA = 25°C
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OCR Scan
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SN74LVC10
SCAS284
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PDF
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