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    POSTED CAS JEDEC Search Results

    POSTED CAS JEDEC Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    ML4800CP Rochester Electronics LLC 1A POWER FACTOR CONTROLLER WITH POST REGULATOR, 250kHz SWITCHING FREQ-MAX, PDIP16, PLASTIC, DIP-16 Visit Rochester Electronics LLC Buy
    10125023-000820BLF Amphenol Communications Solutions HPCE BTB VT Receptacle 8P20S With guide post Visit Amphenol Communications Solutions
    10129651-001LF Amphenol Communications Solutions HPCE BTB R/A Receptacle 36P With guide post Visit Amphenol Communications Solutions
    10129651-005LF Amphenol Communications Solutions HPCE BTB R/A Receptacle 36P With guide post Visit Amphenol Communications Solutions
    10136289-111LF Amphenol Communications Solutions Minitek® Pwr 4.2 HCC, Receptacle Terminal, Gold Flash plating, AWG (#16-20), Post-plating. Visit Amphenol Communications Solutions

    POSTED CAS JEDEC Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    W3H32M72E-XSBX

    Abstract: calibration definition
    Text: White Electronic Designs W3H32M72E-XSBX PRELIMINARY* 32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package FEATURES Data rate = 667*, 533, 400 Programmable CAS latency: 3, 4, 5, or 6 Package: Posted CAS additive latency: 0, 1, 2, 3 or 4 • 208 Plastic Ball Grid Array PBGA , 18 x 20mm


    Original     		W3H32M72E-XSBX W3H32M72E-XSBX calibration definition PDF

    W3H64M72E-XSBX

    Abstract: No abstract text available
    Text: White Electronic Designs W3H64M72E-XSBX ADVANCED* 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package FEATURES Data rate = 667*, 533, 400 Programmable CAS latency: 3, 4 or 5 Package: Posted CAS additive latency: 0, 1, 2, 3 or 4 • 208 Plastic Ball Grid Array PBGA , 17 x 23mm


    Original     		W3H64M72E-XSBX W3H64M72E-XSBX PDF

    Untitled

    Abstract: No abstract text available
    Text: White Electronic Designs W3H64M72E-XSBX 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package FEATURES „ Data rate = 667, 533, 400 „ Programmable CAS latency: 3, 4 or 5 „ Package: „ Posted CAS additive latency: 0, 1, 2, 3 or 4 • 208 Plastic Ball Grid Array PBGA , 16 x 22mm


    Original     		W3H64M72E-XSBX 667Mbs PDF

    Untitled

    Abstract: No abstract text available
    Text: White Electronic Designs W3H64M72E-XSBX ADVANCED* 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package FEATURES „ Data rate = 667*, 533, 400 „ Programmable CAS latency: 3, 4 or 5 „ Package: „ Posted CAS additive latency: 0, 1, 2, 3 or 4 • 208 Plastic Ball Grid Array PBGA , 17 x 23mm


    Original     		W3H64M72E-XSBX PDF

    Untitled

    Abstract: No abstract text available
    Text: White Electronic Designs W3H32M72E-XSBX PRELIMINARY* 32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package FEATURES „ Data rate = 667, 533, 400 „ Programmable CAS latency: 3, 4, 5, or 6 „ Package: „ Posted CAS additive latency: 0, 1, 2, 3 or 4 • 208 Plastic Ball Grid Array PBGA , 18 x 20mm


    Original     		W3H32M72E-XSBX W3H32M72E-XSBX 667Mbs PDF

    W3H32M72E

    Abstract: BA0BA12
    Text: White Electronic Designs W3H32M72E-XSBX 32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package FEATURES  Data rate = 667, 533, 400  Programmable CAS latency: 3, 4, 5, or 6  Package:  Posted CAS additive latency: 0, 1, 2, 3 or 4 • 208 Plastic Ball Grid Array PBGA , 18 x 20mm


    Original     		W3H32M72E-XSBX 667Mbs 533Mbs) 650ps, -550ps, 500ps. W3H32M72E BA0BA12 PDF

    Untitled

    Abstract: No abstract text available
    Text: White Electronic Designs W3H64M72E-XSBX PRELIMINARY* 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package FEATURES „ Data rate = 667*, 533, 400 „ Programmable CAS latency: 3, 4 or 5 „ Package: „ Posted CAS additive latency: 0, 1, 2, 3 or 4 • 208 Plastic Ball Grid Array PBGA , 16 x 22mm


    Original     		W3H64M72E-XSBX PDF

    W3H32M72E

    Abstract: No abstract text available
    Text: White Electronic Designs W3H32M72E-XSB2X Preliminary 32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package FEATURES  Data rate = 667, 533, 400  Programmable CAS latency: 3, 4, 5, or 6  Package:  Posted CAS additive latency: 0, 1, 2, 3 or 4 • 208 Plastic Ball Grid Array PBGA , 16 x 20mm


    Original     		W3H32M72E-XSB2X W3H32M72E PDF

    Untitled

    Abstract: No abstract text available
    Text: White Electronic Designs W3H32M72E-XSBX * 32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package FEATURES „ Data rate = 667, 533, 400 „ Programmable CAS latency: 3, 4, 5, or 6 „ Package: „ Posted CAS additive latency: 0, 1, 2, 3 or 4 • 208 Plastic Ball Grid Array PBGA , 18 x 20mm


    Original     		W3H32M72E-XSBX 667Mbs PDF

    Untitled

    Abstract: No abstract text available
    Text: White Electronic Designs W3H64M72E-XSBX ADVANCED* 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package FEATURES „ Data rate = 667*, 533, 400 „ Programmable CAS latency: 3, 4 or 5 „ Package: „ Posted CAS additive latency: 0, 1, 2, 3 or 4 • 208 Plastic Ball Grid Array PBGA , 16 x 22mm


    Original     		W3H64M72E-XSBX PDF

    Untitled

    Abstract: No abstract text available
    Text: White Electronic Designs W3H32M72E-XSBX PRELIMINARY* 32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package FEATURES „ Data rate = 667, 533, 400 „ Programmable CAS latency: 3, 4, 5, or 6 „ Package: „ Posted CAS additive latency: 0, 1, 2, 3 or 4 • 208 Plastic Ball Grid Array PBGA , 18 x 20mm


    Original     		W3H32M72E-XSBX 667Mbs PDF

    W3H128M72ER-XSBX

    Abstract: M2 8gb pinout
    Text: White Electronic Designs W3H128M72ER-XSBX PRELIMINARY* 128M x 72 REGISTERED DDR2 SDRAM 255 PBGA FEATURES „ Data rate = 667, 533, 400 Mb/s „ Posted CAS additive latency: 0, 1, 2, 3 or 4 „ Package: „ Write latency = Read latency - 1* tCK „ Commercial, Industrial and Military Temperature


    Original     		W3H128M72ER-XSBX W3H128M72ER-XSBX M2 8gb pinout PDF

    W3H128M72ER-XSBX

    Abstract: LDM-1 W3H128M72
    Text: White Electronic Designs W3H128M72ER-XNBX PRELIMINARY* 128M x 72 REGISTERED DDR2 SDRAM 255 PBGA FEATURES  Data rate = 667, 533, 400 Mb/s  Posted CAS additive latency: 0, 1, 2, 3 or 4  Package:  Write latency = Read latency - 1* tCK  Commercial, Industrial and Military Temperature


    Original     		W3H128M72ER-XNBX W3H128M72ER-XSBX LDM-1 W3H128M72 PDF

    icc20

    Abstract: No abstract text available
    Text: White Electronic Designs W3H128M64E-XSBX ADVANCED* 128M x 64 DDR2 SDRAM 208 PBGA Multi-Chip Package FEATURES „ Data rate = 667, 533, 400 Mb/s „ Posted CAS additive latency: 0, 1, 2, 3 or 4 „ Package: „ Write latency = Read latency - 1* tCK • 208 Plastic Ball Grid Array PBGA , 16 x 22mm


    Original     		W3H128M64E-XSBX W3H128M64E-XSBX CL4-ICC20 icc20 PDF

    W3H128M72ER-XSBX

    Abstract: 74sstu32864
    Text: White Electronic Designs W3H128M72ER-XSBX ADVANCED* 128M x 72 REGISTERED DDR2 SDRAM 255 PBGA FEATURES „ Data rate = 667, 533, 400 „ Package: „ CK/CK# Termination options available • 0 ohm, 20 ohm • 255 Plastic Ball Grid Array PBGA , 22 x 26mm „ Posted CAS additive latency: 0, 1, 2, 3 or 4


    Original     		W3H128M72ER-XSBX W3H128M72ER-XSBX 74sstu32864 PDF

    Untitled

    Abstract: No abstract text available
    Text: White Electronic Designs W3H128M72E-XNBX ADVANCED* 128M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package FEATURES „ Data rate = 667, 533, 400 Mb/s „ Posted CAS additive latency: 0, 1, 2, 3 or 4 „ Package: „ Write latency = Read latency - 1* tCK • 208 Plastic Ball Grid Array PBGA , 16 x 22mm


    Original     		W3H128M72E-XNBX PDF

    W3H128M72E-XSBX

    Abstract: No abstract text available
    Text: White Electronic Designs W3H128M72E-XSBX 128M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package FEATURES „ Data rate = 667, 533, 400 „ Package: „ CK/CK# Termination options available • 0 ohm, 20 ohm • 208 Plastic Ball Grid Array PBGA , 16 x 22mm „ Posted CAS additive latency: 0, 1, 2, 3 or 4


    Original     		W3H128M72E-XSBX W3H128M72E-XSBX PDF

    W3H128M72E-XSBX

    Abstract: 84 FBGA
    Text: White Electronic Designs W3H128M72E-XSBX 128M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package FEATURES  Data rate = 667, 533, 400  Package:  CK/CK# Termination options available • 0 ohm, 20 ohm • 208 Plastic Ball Grid Array PBGA , 16 x 22mm  Posted CAS additive latency: 0, 1, 2, 3 or 4


    Original     		W3H128M72E-XSBX 775mA 975mA -100ps 250ps 350ps 400ps W3H128M72E-XSBX 84 FBGA PDF

    Untitled

    Abstract: No abstract text available
    Text: ESM T M14D1G1664A 2D 7DDR II SDRAM 8M x 16 Bit x 8 Banks DDR II SDRAM Features  JEDEC Standard  VDD = 1.8V  Internal pipelined double-data-rate architecture; two data access per clock cycle  Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation.


    Original     		M14D1G1664A PDF

    M14D5121632A

    Abstract: M14D512
    Text: ESMT Preliminary M14D5121632A (2T) DDR II SDRAM 8M x 16 Bit x 4 Banks DDR II SDRAM Features z JEDEC Standard z VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V z Internal pipelined double-data-rate architecture; two data access per clock cycle z Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation.


    Original     		M14D5121632A M14D5121632A M14D512 PDF

    Untitled

    Abstract: No abstract text available
    Text: ESM T M14D2561616A 2L (Preliminary) DDR II SDRAM 4M x 16 Bit x 4 Banks DDR II SDRAM Features JEDEC Standard VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V Internal pipelined double-data-rate architecture; two data access per clock cycle Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation.


    Original     		M14D2561616A PDF

    M14D256

    Abstract: No abstract text available
    Text: ESMT Preliminary M14D2561616A (2L) DDR II SDRAM 4M x 16 Bit x 4 Banks DDR II SDRAM Features z JEDEC Standard z VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V z Internal pipelined double-data-rate architecture; two data access per clock cycle z Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation.


    Original     		M14D2561616A M14D256 PDF

    Untitled

    Abstract: No abstract text available
    Text: ESM T M14D128168A 2M DDR II SDRAM 2M x 16 Bit x 4 Banks DDR II SDRAM Features  JEDEC Standard  VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V  Internal pipelined double-data-rate architecture; two data access per clock cycle  Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation.


    Original     		M14D128168A PDF

    M14D1G166

    Abstract: m14d1g M14D1G1664A m14d1g16 DDRII esmt
    Text: ESMT M14D1G1664A 2D 7DDR II SDRAM 8M x 16 Bit x 8 Banks DDR II SDRAM Features  JEDEC Standard  VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V  Internal pipelined double-data-rate architecture; two data access per clock cycle  Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation.


    Original     		M14D1G1664A M14D1G166 m14d1g M14D1G1664A m14d1g16 DDRII esmt PDF