dm38
Abstract: DM25L F1020 DQ35L0 DM31
Text: Pin Information for the Stratix II EP2S130 Device Version 2.2 Note 1 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 VREFB2N0 VREFB2N0 VREFB2N0
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EP2S130
PT-EP2S130-2
dm38
DM25L
F1020
DQ35L0
DM31
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DM47L
Abstract: aw7 diode EP2S180 F1020 DM55L DM31T DM18B DM17B DM52L DM25L
Text: Pin Information for the Stratix II EP2S180 Device Version 2.2 Note 1 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0
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EP2S180
PT-EP2S180-2
DM47L
aw7 diode
F1020
DM55L
DM31T
DM18B
DM17B
DM52L
DM25L
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BE5L
Abstract: CYD18S18V18 CYD09S36V18 CYD18S36V18 SKR 175 FullFlex36
Text: FullFlex FullFlex Synchronous SDR Dual Port SRAM Features Functional Description • True dual port memory enables simultaneous access to the shared array from each port ■ Synchronous pipelined operation with Single Data Rate SDR operation on each port
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FullFlex36
Abstract: No abstract text available
Text: PRELIMINARY FullFlex Synchronous DDR Dual-Port SRAM Features • True dual-ported memory allows simultaneous access to the shared array from each port • Synchronous pipelined operation with selectable Double Data Rate DDR or Single Data Rate (SDR) operation on each port
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36-Gb/s
484-ball
256-ball
FullFlex72
CYDD36S72V18)
CYDD18S72V18
XS36V18
CYDXXS18V18
BW256
FullFlex36
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FullFlex36
Abstract: No abstract text available
Text: CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 FullFlex Synchronous SDR Dual Port SRAM FullFlex™ Synchronous SDR Dual Port SRAM Features Functional Description • True dual port memory enables simultaneous access the shared array from each port ■ Synchronous pipelined operation with single data rate SDR
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CYDXXS72V18
CYDXXS36V18
CYDXXS18V18
18-Mbit,
36-Mbit
FullFlex72
72-bit
FullFlex36
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Untitled
Abstract: No abstract text available
Text: CYD04S72V CYD09S72V CYD18S72V FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM Functional Description Features • True dual-ported memory cells that allow simultaneous access of the same memory location ■ Synchronous pipelined operation ■ Family of 4 Mbit, 9 Mbit, and 18 Mbit devices
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CYD04S72V
CYD09S72V
CYD18S72V
FLEx72â
64K/128K/256K
18-micron
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DM13B
Abstract: DM15B EP2S90 F1020 DM11R DM10B DQ10B2 DQ15B2 DQ32L2
Text: Pin Information for the Stratix II EP2S90 Device Version 2.4 Note 1 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2
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EP2S90
PT-EP2S90-2
DM13B
DM15B
F1020
DM11R
DM10B
DQ10B2
DQ15B2
DQ32L2
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BE5L
Abstract: CYD04S72V CYD09S72V CYD18S72V DQ60L
Text: CYD04S72V CYD09S72V CYD18S72V FLEx72 3.3 V 64 K/128 K/256 K x 72 Synchronous Dual-Port RAM Functional Description Features • True dual-ported memory cells that allow simultaneous access of the same memory location ■ Synchronous pipelined operation
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CYD04S72V
CYD09S72V
CYD18S72V
FLEx72TM
K/128
K/256
18-micron
BE5L
CYD04S72V
CYD09S72V
CYD18S72V
DQ60L
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FullFlex36
Abstract: CYDXXS36V18 400 OHM RESISTOR DQ67
Text: CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 FullFlex Synchronous SDR Dual Port SRAM FullFlex™ Synchronous SDR Dual Port SRAM Features Functional Description • True dual port memory enables simultaneous access the shared array from each port ■ Synchronous pipelined operation with single data rate SDR
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CYDXXS72V18
CYDXXS36V18
CYDXXS18V18
18-Mbit,
36-Mbit
FullFlex72
72-bit
FullFlex36
400 OHM RESISTOR
DQ67
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DQ12-DQ15
Abstract: CYDXXS36V18 16-SD FullFlex36
Text: PRELIMINARY FullFlex Synchronous DDR Dual-Port SRAM Features • True dual-ported memory allows simultaneous access to the shared array from each port • Synchronous pipelined operation with selectable Double Data Rate DDR or Single Data Rate (SDR) operation on each port
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18-Mbit,
36-Mbit
CYDXXS36V18
CYDXXS18V18
256-Ball
BW256
FullFlex36
484-ball
FullFlex18
DQ12-DQ15
16-SD
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be5l
Abstract: CYD18S72V-133BBI CYD04S72V CYD09S72V CYD18S72V
Text: CYD04S72V CYD09S72V CYD18S72V FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM Features Functional Description • True dual-ported memory cells that allow simultaneous access of the same memory location The FLEx72 family includes 4-Mbit, 9-Mbit and 18-Mbit
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CYD04S72V
CYD09S72V
CYD18S72V
FLEx72TM
64K/128K/256K
FLEx72
18-Mbit
18-Mbit
CYD09S72V
CYDxxS72AV
be5l
CYD18S72V-133BBI
CYD04S72V
CYD18S72V
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FullFlex36
Abstract: No abstract text available
Text: CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 FullFlex Synchronous SDR Dual Port SRAM FullFlex™ Synchronous SDR Dual Port SRAM Features Functional Description • True dual port memory enables simultaneous access the shared array from each port ■ Synchronous pipelined operation with single data rate SDR
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CYDXXS72V18
CYDXXS36V18
CYDXXS18V18
72-bit
484-ball
256-ball
FullFlex36
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CYD18S72V-133BBI
Abstract: CYD04S72V CYD09S72V CYD18S72V BE6R DQ49L
Text: CYD04S72V CYD09S72V CYD18S72V FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM Features Functional Description • True dual-ported memory cells that allow simultaneous access of the same memory location The FLEx72 family includes 4-Mbit, 9-Mbit and 18-Mbit
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CYD04S72V
CYD09S72V
CYD18S72V
FLEx72TM
64K/128K/256K
FLEx72
18-Mbit
18-Mbit
CYD09S72V
CYDxxS72AV
CYD18S72V-133BBI
CYD04S72V
CYD18S72V
BE6R
DQ49L
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0c002
Abstract: BE5L CYD18S72V-100BBC BE4L
Text: PRELIMINARY FLEx72TM 18-Mb 256K x 72 Synchronous Dual-Port RAM Seamless Migration to Next-Generation FLEx72-ETM 18-Mb Dual-Port (CYD18S72V18) Features FLEx72TM (CYD18S72V) • True dual-ported memory allows both ports to simultaneously read from the same memory location
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FLEx72TM
18-Mb
FLEx72TM
CYD18S72V)
18-Mb
133-MHz
484-ball
BB484
FLEx72-E
0c002
BE5L
CYD18S72V-100BBC
BE4L
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be5l
Abstract: No abstract text available
Text: CYD04S72V CYD09S72V CYD18S72AV FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM Features Functional Description • True dual-ported memory cells that allow simultaneous access of the same memory location The FLEx72™ family includes 4-Mbit, 9-Mbit and 18-Mbit
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CYD04S72V
CYD09S72V
CYD18S72AV
FLEx72TM
64K/128K/256K
18-Mbit
18-micron
484-ball
CYD18S72AV
be5l
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FullFlex36
Abstract: DQ67L CYD18S72V18
Text: FullFlex FullFlexTM Synchronous SDR Dual Port SRAM FullFlex Synchronous SDR Dual Port SRAM Features Functional Description • True dual port memory enables simultaneous access to the shared array from each port ■ Synchronous pipelined operation with single data rate SDR
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18-Mbit,
36-Mbit
FullFlex72
72-bit
FullFlex36
DQ67L
CYD18S72V18
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Untitled
Abstract: No abstract text available
Text: CYD09S72V CYD18S72V FLEx72 3.3 V 128 K/256 K x 72 Synchronous Dual-Port RAM Features Functional Description • True dual-ported memory cells that allow simultaneous access of the same memory location ■ Synchronous pipelined operation ■ Family of 9-Mbit, and 18-Mbit devices
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CYD09S72V
CYD18S72V
FLEx72â
K/256
18-Mbit
18-micron
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FullFlex36
Abstract: CYD04S36V18 CYD09S36V18 CYD18S18V18 CYD18S36V18
Text: FullFlex FullFlexTM Synchronous SDR Dual Port SRAM FullFlex Synchronous SDR Dual Port SRAM Features Functional Description • True dual port memory enables simultaneous access to the shared array from each port ■ Synchronous pipelined operation with single data rate SDR
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72-bit
484-ball
256-ball
FullFlex72
36-Mbit:
CYD36S72V18)
18-Mbit:
CYD18ation
FullFlex36
CYD04S36V18
CYD09S36V18
CYD18S18V18
CYD18S36V18
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FullFlex36
Abstract: No abstract text available
Text: CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 FullFlex Synchronous SDR Dual Port SRAM FullFlex™ Synchronous SDR Dual Port SRAM Features Functional Description • True dual port memory enables simultaneous access the shared array from each port ■ Synchronous pipelined operation with single data rate SDR
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CYDXXS72V18
CYDXXS36V18
CYDXXS18V18
72-bit
18-Mbit,
36-Mbit
FullFlex36
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CYD18S18V18-200BBAXI
Abstract: FullFlex36 CYD36S18V18-167BGXI
Text: FullFlex FullFlex Synchronous SDR Dual Port SRAM Features Functional Description • True dual port memory enables simultaneous access to the shared array from each port ■ Synchronous pipelined operation with single data rate SDR operation on each port
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FullFlex72
72-bit
CYD18S18V18-200BBAXI
FullFlex36
CYD36S18V18-167BGXI
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Untitled
Abstract: No abstract text available
Text: CYD04S72V CYD09S72V CYD18S72V FLEx72 3.3 V 64 K/128 K/256 K x 72 Synchronous Dual-Port RAM Functional Description Features • True dual-ported memory cells that allow simultaneous access of the same memory location ■ Synchronous pipelined operation
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CYD04S72V
CYD09S72V
CYD18S72V
FLEx72TM
K/128
K/256
FLEx72
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be5l
Abstract: CYD04S72V CYD09S72V CYD18S72V
Text: CYD04S72V CYD09S72V CYD18S72V FLEx72 3.3 V 64 K/128 K/256 K x 72 Synchronous Dual-Port RAM Features Functional Description • True dual-ported memory cells that allow simultaneous access of the same memory location ■ Synchronous pipelined operation
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CYD04S72V
CYD09S72V
CYD18S72V
FLEx72TM
K/128
K/256
FLEx72
be5l
CYD04S72V
CYD09S72V
CYD18S72V
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FullFlex36
Abstract: CYD09S36V18 CYD18S18V18 CYD18S36V18
Text: FullFlex FullFlexTM Synchronous SDR Dual Port SRAM FullFlex Synchronous SDR Dual Port SRAM Features Functional Description • True dual port memory enables simultaneous access the shared array from each port ■ Synchronous pipelined operation with single data rate SDR
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72-bit
18-Mbit,
36-Mbit
FullFlex36
CYD09S36V18
CYD18S18V18
CYD18S36V18
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14517B
Abstract: DQ41R d05r 13912B
Text: o rm \ss n~n n R/C-B ASS’YLAYOUT o ¡J EE £ El EE IE EE EE El yym K4H2B083&*-T# sec El El korea EE EE O O EE n~~n 1 n~n n SEC KOREA y y M l K4H20083&^-T# rm RRRRRRRRRRRRRRRHRRRRRRHRRRRRRHnRR EE EE SEC KOREA YYW W K4 H28Q838*-T# ozo o o rm . rm im o EE
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OCR Scan
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50-DIMM
50-DINN
14517B
DQ41R
d05r
13912B
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