bang bang phase detector
Abstract: GD16584 GD16585 DO13 package DO15 GD16588 STM-64 HCGD16588-EF
Text: 10 Gbit/s Receiver, CDR and DeMUX GD16584/GD16588 FEC an Intel company Preliminary General Description Features GD16584 and GD16588 are Receiver chips for use in STM-64/192 and Optical Transport Networking (OTN) systems. The component is available in two versions:
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GD16584/GD16588
GD16584
GD16588
STM-64/192
bang bang phase detector
GD16585
DO13 package
DO15
STM-64
HCGD16588-EF
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GD16544
Abstract: metal detector plans AD8042 DO15 STM-64
Text: 10 Gbit/s Receiver, CDR and DeMUX GD16544 an Intel company Preliminary General Description Features GD16544 is a 9.95328 Gbit/s Receiver chip for use in SDH STM-64 and SONET OC-192 optical communication systems. GD16544 is a Clock and Data Recovery IC with:
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GD16544
GD16544
STM-64
OC-192
metal detector plans
AD8042
DO15
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GD16585
Abstract: bang bang phase detector DO15 GD16584 GD16588 STM-64
Text: 10 Gbit/s Receiver, CDR and DeMUX GD16584/GD16588 FEC an Intel company Preliminary General Description Features GD16584 and GD16588 are Receiver chips for use in STM-64/192 and Optical Transport Networking (OTN) systems. The component is available in two versions:
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GD16584/GD16588
GD16584
GD16588
STM-64/192
GD16585
bang bang phase detector
DO15
STM-64
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GD16585
Abstract: GD16588-EB bang bang phase detector DO15 GD16584 GD16588 STM-64 9G49
Text: 10 Gbit/s Receiver, CDR and DeMUX GD16584/GD16588 FEC Preliminary General Description Features GD16584 and GD16588 are Receiver chips for use in STM-64/192 and Optical Transport Networking (OTN) systems. The component is available in two versions: u GD16584 for 9.5328 Gbit/s.
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GD16584/GD16588
GD16584
GD16588
STM-64/192
DK-2740
GD16585
GD16588-EB
bang bang phase detector
DO15
STM-64
9G49
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intel 7882
Abstract: 31 anl DO15 GD16524 STM16 STM-16
Text: 2.5 Gbit/s Clock and Data Recovery and 1:16 DeMUX GD16524 an Intel company General Description Features The CDR contains all circuits needed for reliable acquisition and lock of the VCO phase to the incoming data-stream. The electrical input sensitivity is better
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GD16524
GD16524
STM-16
OC-48
intel 7882
31 anl
DO15
STM16
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DO13 package
Abstract: DO14 DO15 GD16524 STM16 STM-16
Text: 2.5 Gbit/s Clock and Data Recovery GD16524 an Intel company Preliminary General Description Features The electrical input sensitivity is better than 8 mV BER <10-10 . The GD16524 is a high performance monolithic integrated multi-rate Clock and Data Recovery (CDR) device applicable for optical communication systems
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GD16524
GD16524
STM-16
OC-48
DK-2740
DO13 package
DO14
DO15
STM16
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op-amp integrator mhz
Abstract: DO13 package metal detector plans AD8042 DO15 GD16544 STM-64 GD16555
Text: 10 Gbit/s Receiver, CDR and DeMUX GD16544 Preliminary General Description Features GD16544 is a 9.95328 Gbit/s Receiver chip for use in SDH STM-64 and SONET OC-192 optical communication systems. GD16544 is a Clock and Data Recovery IC with: u an on-chip VCO
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GD16544
GD16544
DK-2740
op-amp integrator mhz
DO13 package
metal detector plans
AD8042
DO15
STM-64
GD16555
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Untitled
Abstract: No abstract text available
Text: TA8401F FUNCTIONAL BRIDGE DRIVER. . Wide operating Supply Voltage Range : Vccopr MIN =3V . Capsealed in Flat Package 16 pin. . Forward and Reverse Rotation, Short Breke Modes are Available by Means of Rotation Control Signals. . High Efficiency is Obtained.
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TA8401F
-500mA)
-25mA)
Don11
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kcd3
Abstract: UPD6121f PD17012GF KT77 7012GF 51I7 KVF1 FC-7 3P ks-49 KTVA
Text: T — $ • S '— h S M O S * a iilS & M O S In te g ra te d C ircuit j t t P D 1 i f * (M W FM, MW , L W f i - t P L U a * lB ^ 7 <fc * > ' : ] > 1 2 G F - 5 3 m h P - 7 AiP D 1 7 0 1 2 G F -0 5 3 ti^ # ^ f& < 7 P L L JiiÈ S '> > -tri# -< 1 f^ F M > MW, L W* . ! —
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LW31J.
OAM77
kcd3
UPD6121f
PD17012GF
KT77
7012GF
51I7
KVF1
FC-7 3P
ks-49
KTVA
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Untitled
Abstract: No abstract text available
Text: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT 64M-BIT VIRTUAL CHANNEL SDRAM SINGLE DATA RATE 64M-BIT VIRTUAL CHANNEL SDRAM VERSION 1.1 Description The 64 Mbit Virtual Channel VC SDRAM is implemented to be 100% pin and package compatible to the industry standard SDRAM. It uses the same command protocol and interface as SDRAM. The VC SDRAM command set is a
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64M-BIT
S54G5-80-9JF
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Untitled
Abstract: No abstract text available
Text: DA TA SH EE T NEC MOS INTEGRATED CIRCUIT ¿¿PD4565421,4565821, 4565161 64M-BIT VIRTUAL CHANNEL SDRAM Description The 64M -bit Virtual Channel VC SDRAM is implemented to be 100% pin and package compatible to the industry standard SDRAM. It uses the same command protocol and interface as SDRAM. The VC SDRAM command set is a
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PD4565421
64M-BIT
M13022EJBV0DS00
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qml-38535
Abstract: QML-38534 CQCC1-N20 GDFP2-F16 GDIP1-T16
Text: REVISIONS DATE DESCRIPTION LTR APPROVED Y R - M O - D A REV SHEET REV SHEET REV STATUS OF SHEETS PMIC N/A STANDARDIZED MILITARY DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A REV 10 SHEET
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5962-E232-93
QML-38535.
QML-38535
MIL-BUL-103.
MIL-BUL-103
QPL-38510
QML-38534
CQCC1-N20
GDFP2-F16
GDIP1-T16
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M5M416100BJ
Abstract: No abstract text available
Text: V ~ ? V ? 'S V ' . w p u N ^ M 5 M 4 1 6 1 0 0 B J ,T P ,R T -5 , * e U 6 ‘J ? ' s -7 , - 5 S r 6 S ,-7 S FAST PAGE MODE 16777216-BIT 16777216-WORD BY 1-Bn DYNAMIC RAM DESCRIPTION This is a family of 16777216-word by 1-bit dynamic RAMS, abricated with the high performance CMOS process,and is ideal
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16777216-BIT
16777216-WORD
M5M416100BJ
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D17012GF
Abstract: 78MEC D17012GF-011 D17012G ltaft et 4-1-fm bfy40 d17012 tlu 011 uPD6121G
Text: i r — • ts— h Ü 5 È M O S Â « @ £ & N E M O S Integrateci Circuit C j F M , M P L L J l ) W Æ u , L W S è v P 1 D f n - t > i r 7 (¥ # c ) - 9 - < 1 2 G F - 1 1 m h P “ 7 >u P D 1 7 0 1 2 G F -0 1 1 {â ^ :tâ :^ lÆ iiO P L L jl> ra '> > iz -y -< 1 f^ ïfc F M ) MW, L W if
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//PD17012GF-011
200MHz7Â
TFM18j^
D17012GF
78MEC
D17012GF-011
D17012G
ltaft
et 4-1-fm
bfy40
d17012
tlu 011
uPD6121G
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M5M418160DJ
Abstract: No abstract text available
Text: I Pm ììm ìm ry S p e c. MITSUBISHI LSIs MH2M32DXJ/DNXJ-5,-6,-7 FAST PAGE MODE 33554432-BIT 1048576-WORD BY 32-BIT DYNAMIC RAM PIN CONFIGURATION (TOP VIEW) [Single side] DESCRIPTION The MH2M32DXJ/DNXJ is 2097152-word x 32-biîs dynamic RAM. This consists of four industry standard 1M x 16 dynamic
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MH2M32DXJ/DNXJ-5
33554432-BIT
1048576-WORD
32-BIT
MH2M32DXJ/DNXJ
2097152-word
32-bi
39-Vss
MT-DT-0200-0
Jul/23/1998
M5M418160DJ
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33554432-BIT
Abstract: MIT-DS-0321-0 MH1M325
Text: M ITS UBS HI LS b MH1 M325DXJ/DNXJ-5,-6,-7 HYPER PAGE MODE 33554432-BIT < «W8576-WORD BY 32-BfT DYNAMIC RAM PIN CONFIGURATION TOP VIEW) [Single side] DESCRIPTION The MH1 M 325CXJ/CNXJ is 1048576-word x 32-bits dynamic RAM. This consists of two industry standard 1 M x16 dynamic
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M325DXJ/DNXJ-5
33554432-BIT
W8576-WORD
32-BfT)
325CXJ/CNXJ
1048576-word
32-bits
MH1M325DXJ/DNXJ-6
Jul/23/1998
MIT-DS-0321-0
MH1M325
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MH8M325D
Abstract: No abstract text available
Text: I PmUmm&ry Spm:. MITSUBISHI LSls MH8M325DJ/DNJ-5,-6,-7 HYPER PAGE MODE 268435456-BIT 8388608-WQRD BY 32-BIT DYNAMIC RAM PIN CONFIGURATION (TOP VIEW) [Double side] DESCRIPTION The MH8M325DJ/DNJ is 8388608 -word x 32-bits dynamic RAM. This consists of sixteen industry standard 4M x 4 dynamic
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MH8M325DJ/DNJ-5
268435456-BIT
8388608-WQRD
32-BIT
MH8M325DJ/DNJ
32-bits
MH8M325D
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m5m416405
Abstract: M5M416405CJ
Text: M IT S U B IS H I L S ls p r e l i m i n a r M5M416405CJ ,TP-5,-6,-7, -5S,-6S,-7S HYPER PAGE MODE 16777216-BIT 4194304-WORD BY 4-BIT DYNAMIC RAM DESCRIPTION PIN CONFIGURATION (TOP VIEW) This is a family of 4194304-word by 4-bit dynamic RAMs with Hyper Page mode fuction, fabricated with the high performance
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M5M416405CJ
16777216-BIT
4194304-WORD
M5M416405CJ
4194304-WQRD
m5m416405
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Untitled
Abstract: No abstract text available
Text: HM534251 Series 262,144 x 4-Bit Multiport CMOS Video Random Access Memory • DESCRIPTION HM534251JP Series The HM534251 is a 1-Mbit multiport video RAM equipped with a 256k-word x 4-bit dynamic RAM and a 512-word x 4-bit SAM serial access memory . Its RAM
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HM534251
256k-word
512-word
HM534251JP
ns/100
ns/120
ns/150
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Untitled
Abstract: No abstract text available
Text: MITSUBISHI LSIs M 5 M 4 1 6 1 0 0 B J ,T P -5 ,- 6 ,-7 FAST PAGE MODE 16777216-BIT 16777216-WORD BY 1-BIT DYNAMIC RAM DESCRIPTION PIN CONFIGURATION (TOP VIEW) This is a family of 16777216-word by 1-bit dynamic RAMS, fabricated with the high performance CMOS process,and is ideal
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16777216-BIT
16777216-WORD
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Untitled
Abstract: No abstract text available
Text: MITSUBISHI LSIs M5M4V4265CTP-6,-7,-6S,-7S EDO HYPER PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM DESCRIPTION PIN CONFIGURATION (TOP VIEW) This is a family of 262144-word by 16-bit dynamic RAMs with Hyper page mode fuction, fabricated with the high performance
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M5M4V4265CTP-6
4194304-BIT
262144-WORD
16-BIT)
16-bit
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TC524256
Abstract: tc524256z
Text: TOSHIBA MOS MEMORY PRODUCTS TC524256P/Z/J-10, TC524256P/Z/J-12 DESCRIPTION The TC524256P/Z/J is a CMOS Multiport memory equipped with a 262,144-wordx 4 bit dynamic random access memory RAM port and a 512-word * 4 bit static serial access memory(SAM) port.
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TC524256P/Z/J-10,
TC524256P/Z/J-12
TC524256P/Z/J
144-wordx
512-word
TC524256
tc524256z
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Untitled
Abstract: No abstract text available
Text: DA TA SH EE T MOS INTEGRATED CIRCUIT ¿iPD4565421, 4565821, 4565161 64M-BIT VIRTUAL CHANNEL SDRAM Description The 64M -bit Virtual Channel VC SDRAM is im plem ented to be 100% pin and package compatible to the industry standard SDRAM. It uses the same command protocol and interface as SDRAM. The VC SDRAM command set is a
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iPD4565421,
64M-BIT
M13022EJAV0DS00
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Untitled
Abstract: No abstract text available
Text: HM4864ACG-12, HM4864ACG-15, HM4864ACG-20 6 5 5 3 6 -word x 1 -b it Dynam ic Random A c c e ss Mem ory • FEATURES • 18-pin Leadless Chip Carrier • • • • Single 5V ±10% On chip substrate bias generator Low Power: 250mW active, 18mW standby Highspeed: Access Time 1 2 0 /1 50/200ns (max)
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HM4864ACG-12,
HM4864ACG-15,
HM4864ACG-20
18-pin
250mW
50/200ns
4864ACG-1
Don11
4864ACG
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