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    38K50 Search Results

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    38K50 Price and Stock

    Vishay Dale CMF55238K50FKEB

    RES 238.5K OHM 1/2W 1% AXIAL
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    DigiKey CMF55238K50FKEB Reel 1,000
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    • 1000 $0.13857
    • 10000 $0.13857
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    VPG Transducers Y14538K50900F9L

    RES 8.509K OHM 0.6W 1% RADIAL
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    DigiKey Y14538K50900F9L Bulk 25
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    • 100 $19.3616
    • 1000 $19.3616
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    Avnet Americas Y14538K50900F9L Bulk 25
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    • 100 $12.006
    • 1000 $9.399
    • 10000 $9.399
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    Vishay Dale CMF55238K50FKR6

    RES 238.5K OHM 1/2W 1% AXIAL
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey CMF55238K50FKR6 Reel 1,000
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    Vishay Dale ALSR038K500JE12

    RES 8.5K OHM 3W 5% AXIAL
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    DigiKey ALSR038K500JE12 Bulk 100
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    • 100 $1.0885
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    RS ALSR038K500JE12 Bulk 100
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    • 100 $1.17
    • 1000 $1.15
    • 10000 $1.14
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    Vishay Intertechnologies CPF38K5000FKB14

    CPF-3 8.5K 1% T-1 B14 - Bulk (Alt: CPF38K5000FKB14)
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    Avnet Americas CPF38K5000FKB14 Bulk 55 Weeks 100
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    • 100 $4.653
    • 1000 $0.77616
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    38K50 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    38K30

    Abstract: DELTA39K
    Text: USE DELTA39K FOR Quantum38K™ ISR™ ALL NEW DESIGNS CPLD Family CPLDs Designed for Migration Features • High density — 30K to 100K usable gates — 512 to 1536 macrocells — 136 to 302 maximum I/O pins — Eight dedicated inputs including four clock pins and


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    PDF DELTA39KTM Quantum38KTM 16-Kb 48-Kb 125-MHz 18-mm Quantum38K30 Quantum38K50 Quantum38K Delta39K 38K30

    100K preset horizontal

    Abstract: LB 124 d LB 124 transistor verilog code for implementation of eeprom 38K30 j510
    Text: Quantum38K ISR™ CPLD Family PRELIMINARY CPLDs Designed for Migration Features • High density — 30K to 100K usable gates — 512 to 1536 macrocells — 136 to 302 maximum I/O pins — Eight Dedicated Inputs including four clock pins and four global I/O control signal pins; four JTAG interface pins for reconfigurability/boundary scan


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    PDF Quantum38KTM CY38K100 208-pin 208EQFP) Quantum38K30 Quantum38K50 Quantum38K 100K preset horizontal LB 124 d LB 124 transistor verilog code for implementation of eeprom 38K30 j510

    vhdl code for dice game

    Abstract: Video Proc 3.3V 0.07A 64-Pin PQFP ez811 GRAPHICAL LCD interfaced with psoc 5 cypress ez-usb AN2131QC CYM9239 vhdl code PN 250 code generator CY3649 cy7c63723 Keyboard and Optical mouse program CY7C9689 ethernet
    Text: Product Selector Guide Communications Products Description Pins Part Number Freq. Range Mbps ICC (mA) Packages* 3.3V SONET/SDH PMD Transceiver 2.5V SiGe Low Power SONET/SDH Transceiver SONET/SDH Transceiver w/ 100K Logic 2.5 G-Link w/ 100K Logic OC-48 Packet Over SONET (POS) Framer


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    PDF OC-48 CYS25G0101DX CYS25G0102 CYS25G01K100 CYP25G01K100 CY7C9536 CY7C955 CY7B952 CY7B951 10BASE vhdl code for dice game Video Proc 3.3V 0.07A 64-Pin PQFP ez811 GRAPHICAL LCD interfaced with psoc 5 cypress ez-usb AN2131QC CYM9239 vhdl code PN 250 code generator CY3649 cy7c63723 Keyboard and Optical mouse program CY7C9689 ethernet

    Untitled

    Abstract: No abstract text available
    Text: Quantum38K ISR™ CPLD Family CPLDs Designed for Migration Features • High density — 30K to 100K usable gates — 512 to 1536 macrocells — 136 to 302 maximum I/O pins — Eight dedicated inputs including four clock pins and four global I/O control signal pins; four JTAG


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    PDF Quantum38Kâ 125-MHz 18-mm Quantum38K30 Quantum38K50 Quantum38K

    Untitled

    Abstract: No abstract text available
    Text: Quantum38K ISR™ CPLD Family PRELIMINARY CPLDs at ASIC Prices™ Features • High density — 30K to 100K usable gates — 512 to 1536 macrocells — 136 to 302 maximum I/O pins — 8 Dedicated Inputs including 4 clock pins and 4 global I/O control signal pins; 4 JTAG interface pins


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    PDF Quantum38KTM 38K15 144FBGA MIL-STD-883" /JESD22-A114-A 83MHz 66MHz" 125MHz 83MHz" Quantum38K

    208EQFP

    Abstract: No abstract text available
    Text: Quantum38K ISR™ CPLD Family CPLDs Designed for Migration Features • High density — 30K to 100K usable gates — 512 to 1536 macrocells — 136 to 302 maximum I/O pins — Eight dedicated inputs including four clock pins and four global I/O control signal pins; four JTAG


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    PDF Quantum38KTM 125-MHz 18-mm Quantum38K30 Quantum38K50 Quantum38K 208EQFP

    CY3LV010

    Abstract: 38K30 CYDH2200E 38K50
    Text: Quantum38K ISR™ CPLD Family PRELIMINARY CPLDs at ASIC Prices™ Features • High density — 30K to 100K usable gates — 512 to 1536 macrocells — 136 to 302 maximum I/O pins — Eight Dedicated Inputs including four clock pins and four global I/O control signal pins; four JTAG interface pins for reconfigurability/boundary scan


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    PDF Quantum38KTM Quantum38K CY38K100 208-pin 208EQFP) CY3LV010 38K30 CYDH2200E 38K50

    WIDE BUS FAMILY

    Abstract: No abstract text available
    Text: Quantum38K ISR™ CPLD Family PRELIMINARY CPLDs at ASIC Prices™ Features • High density — 15K to 100K usable gates — 256 to 1536 macrocells — 92 to 302 maximum I/O pins — 8 Dedicated Inputs including 4 clock pins and 4 global control signal pins; 4 JTAG interface pins for


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    PDF Quantum38KTM WIDE BUS FAMILY

    38K30

    Abstract: DELTA39K CY3LV010
    Text: USE DELTA39K FOR Quantum38K™ ISR™ ALL NEW DESIGNS CPLD Family CPLDs Designed for Migration Features • High density — 30K to 100K usable gates — 512 to 1536 macrocells — 136 to 302 maximum I/O pins — Eight dedicated inputs including four clock pins and


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    PDF DELTA39KTM Quantum38KTM 16-Kb 48-Kb 125-MHz 18-mm Quantum38K30 Quantum38K50 Quantum38K Delta39K 38K30 CY3LV010