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    74LV109

    Abstract: 74LV109D 74LV109DB 74LV109N 74LV109PW
    Text: Philips Semiconductors Preliminary Specification Dual J K flip-flop with set and reset; positive-edge trigger FE A T U R E S • Optim ized for Low Voltage applications: 1.0 to 3.6 V • A cce pts TTL input levels between V cc = 2.7 V and Vcc = 3.6 V • Typical V ou> output ground


    OCR Scan     		74LV109 74LV109 74HC/HCT109. 711062b 0Q7S244 74LV109D 74LV109DB 74LV109N 74LV109PW PDF