This site uses third-party website tracking technologies to provide and continually improve our services, and to display advertisements according to users' interests. I agree and may revoke or change my consent at any time with effect for the future.
CY2SSTV855
Differential Clock Buffer/Driver
Features
· Phase-locked loop (PLL) clock distribution for Double Data Rate Synchronous DRAM applications · 1:5 differential outputs · External feedback p
