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    CY2SSTV855

    Abstract: CY2SSTV855ZC CY2SSTV855ZCT
    Text: TV855 TV855 Differential Clock Buffer/Driver Features Description • Phase-locked loop clock distribution for Double Data Rate Synchronous DRAM applications • 1:5 differential outputs • External feedback pins FBINT, FBINC are used to synchronize the outputs to the clock input


    Original     		TV855 CY2SSTV855 CY2SSTV855 CY2SSTV855ZC CY2SSTV855ZCT PDF

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    Abstract: No abstract text available
    Text: TV855 TV855 Differential Clock Buffer/Driver Features Description • Phase-locked loop clock distribution for Double Data Rate Synchronous DRAM applications • 1:5 differential outputs • External feedback pins FBINT, FBINC are used to synchronize the outputs to the clock input


    Original     		TV855 CY2SSTV855 CY2SSTV855 PDF