TSMC SINGLE PORT SRAM Search Results

TSMC SINGLE PORT SRAM Result Highlights (5)

Part	Manufacturer	Description	Download
FO-9LPBMTRJ00-001	Amphenol Cables on Demand	Amphenol FO-9LPBMTRJ00-001 MT-RJ Connector Loopback Cable: Single-Mode 9/125 Fiber Optic Port Testing .1m	Datasheet
AV-THLIN2RCAM-005	Amphenol Cables on Demand	Amphenol AV-THLIN2RCAM-005 Thin-line Single RCA Coaxial Cable - RCA Male / RCA Male (Coaxial Digital Audio Compatible) 5ft	Datasheet
CS-SASSDP8282-001	Amphenol Cables on Demand	Amphenol CS-SASSDP8282-001 29 position SAS to SATA Drive Connector Single Data Lane Cable 1m	Datasheet
FO-62.5LPBMT0-001	Amphenol Cables on Demand	Amphenol FO-62.5LPBMT0-001 MT-RJ Connector Loopback Cable: Multimode 62.5/125 Fiber Optic Port Testing .1m	Datasheet
SF-SFP28LPB1W-3DB	Amphenol Cables on Demand	Amphenol SF-SFP28LPB1W-3DB SFP28 Loopback Adapter Module for SFP28 Port Compliance Testing - 3dB Attenuation & 1W Power Consumption	Datasheet

TSMC SINGLE PORT SRAM Datasheets Context Search

Catalog Datasheet	MFG & Type	PDF	Document Tags
chn 723 Abstract: TSMC 180nm dual port sram chn 448 CHN 727 chn 501 chn 711 CHN 450 TSMC 180nm single port sram tsmc 180nm sram TSMC 180nm Text: CS4100 TM ADPCM Speech Coders Virtual Components for the Converging World The CS4100 family of adaptive differential pulse code modulators ADPCMs is designed to provide high performance solutions for a broad range of applications requiring speech compression and decompression.	Original	PDF	CS4100 CS4100 DS4100 chn 723 TSMC 180nm dual port sram chn 448 CHN 727 chn 501 chn 711 CHN 450 TSMC 180nm single port sram tsmc 180nm sram TSMC 180nm
AMBA AXI verilog code Abstract: BP140 TSMC single port sram ARM SRAM compiler CL013G AMBA file write AXI verilog code tsmc sram ARM verilog code ARM single port SRAM compiler 16384x32 Text: PrimeCell Infrastructure AMBA 3 AXI Internal Memory Interface BP140 Revision: r0p0 Technical Overview ™ This technical overview describes the functionality of the AXI internal memory interface in the following sections: • Preliminary material on page 2	Original	PDF	BP140) AMBA AXI verilog code BP140 TSMC single port sram ARM SRAM compiler CL013G AMBA file write AXI verilog code tsmc sram ARM verilog code ARM single port SRAM compiler 16384x32
TSMC cmos 0.18um Abstract: TSMC 0.18um SRAM TSMC 180nm single port sram TSMC 180nm dual port sram TSMC 0.18Um tsmc 180nm sram 2 port register file SC18 180-nm TSMC 180nm Text: AMI Semiconductor SC18 0.18µm CMOS Standard Cell SC18 0.18µm CMOS Standard Cell Feature Sheet Key Features • Excellent performance: • 5.6ns delay for an 18 x 18 multiplier • Junction temperature range -40°C to 125°C • AMIS 180nm ASICs provide the optimal combination of	Original	PDF	180nm 200-300MHz 30nW/MHz/gate CL018G PCI33, PCI66, PCIX-183 M-20620-001 TSMC cmos 0.18um TSMC 0.18um SRAM TSMC 180nm single port sram TSMC 180nm dual port sram TSMC 0.18Um tsmc 180nm sram 2 port register file SC18 180-nm TSMC 180nm
CHN 530 Abstract: chn 723 chn 448 CHN 727 CS4125 CS4130 chn 711 TSMC sram1 CS4100 CS4110 Text: CS4100 ADPCM Speech Coders Virtual Components for the Converging World The CS4100 family of adaptive differential pulse code modulators ADPCMs is designed to provide high performance solutions for a broad range of applications requiring speech compression and decompression. These	Original	PDF	CS4100 CS4100 DS4100-b CHN 530 chn 723 chn 448 CHN 727 CS4125 CS4130 chn 711 TSMC sram1 CS4110
TSMC single port sram Abstract: No abstract text available Text: SONY CXK77P36L80GB 8Mb LW R-L HSTL High Speed Synchronous SRAMs 256K x 36 4/42/43/44 Preliminary Description The CXK77P36L80GB is a high speed CMOS synchronous static RAM with common I/O pins, organized as 262,144 words by 36 bits. This synchronous SRAM integrates input registers, high speed RAM, output latches, and a one-deep write buffer	Original	PDF	CXK77P36L80GB CXK77P36L80GB 200mV -100uA TSMC single port sram
CXK77P36L80GB-4A Abstract: CXK77P36R80GB CXK77P36R80GB-33 CXK77P36R80GB-4A Text: SONY CXK77P36R80GB 8Mb LW R-R HSTL High Speed Synchronous SRAM 256K x 36 33/4 Preliminary Description The CXK77P36R80GB is a high speed CMOS synchronous static RAM with common I/O pins, organized as 262,144 words by 36 bits. This synchronous SRAM integrates input registers, high speed RAM, output registers, and a one-deep write buffer	Original	PDF	CXK77P36R80GB CXK77P36R80GB 200mV -100uA CXK77P36L80GB-4A CXK77P36R80GB-33 CXK77P36R80GB-4A
sony tsmc Abstract: CXK77P18L80AGB CXK77P36L80AGB CXK77P36L80AGB-4 CXK77P36L80AGB-4A Text: SONY CXK77P36L80AGB / CXK77P18L80AGB 8Mb LW R-L HSTL High Speed Synchronous SRAMs 256K x 36 or 512K x18 4/42/43/44 Preliminary Description The CXK77P36L80AGB (organized as 262,144 words by 36 bits) and the CXK77P18L80AGB (organized as 524,288 words by 18 bits) are high speed CMOS synchronous static RAMs with common I/O pins. These synchronous SRAMs integrate input	Original	PDF	CXK77P36L80AGB CXK77P18L80AGB CXK77P36L80AGB 200mV -100uA sony tsmc CXK77P18L80AGB CXK77P36L80AGB-4 CXK77P36L80AGB-4A
marking code 43b Abstract: diode marking code 4n tsmc cmos CXK77P36L80GB-42 CXK77P36L80GB-4A CXK77P36L80GB-4B CXK77P36L80GB CXK77P36L80GB-4 Text: SONY  CXK77P36L80GB 8Mb LW R-L HSTL High Speed Synchronous SRAMs 256K x 36 4/42/43/44 Preliminary Description The CXK77P36L80GB is a high speed CMOS synchronous static RAM with common I/O pins, organized as 262,144 words by 36 bits. This synchronous SRAM integrates input registers, high speed RAM, output latches, and a one-deep write buffer	Original	PDF	CXK77P36L80GB CXK77P36L80GB 200mV -100uA marking code 43b diode marking code 4n tsmc cmos CXK77P36L80GB-42 CXK77P36L80GB-4A CXK77P36L80GB-4B CXK77P36L80GB-4
7x17 Abstract: CXK77P18L80AGB CXK77P36L80AGB CXK77P36L80AGB-4 CXK77P36L80AGB-4A Text: SONY CXK77P36L80AGB / CXK77P18L80AGB 8Mb LW R-L HSTL High Speed Synchronous SRAMs 256K x 36 or 512K x18 4/42/43/44 Preliminary Description The CXK77P36L80AGB (organized as 262,144 words by 36 bits) and the CXK77P18L80AGB (organized as 524,288 words by 18 bits) are high speed CMOS synchronous static RAMs with common I/O pins. These synchronous SRAMs integrate input	Original	PDF	CXK77P36L80AGB CXK77P18L80AGB CXK77P36L80AGB 7x17 CXK77P18L80AGB CXK77P36L80AGB-4 CXK77P36L80AGB-4A
CXK77P36R80GB Abstract: CXK77P36R80GB-33 CXK77P36R80GB-37 CXK77P36R80GB-4A Text: SONY CXK77P36R80GB 8Mb LW R-R HSTL High Speed Synchronous SRAM 256K x 36 33/37/4 Preliminary Description The CXK77P36R80GB is a high speed CMOS synchronous static RAM with common I/O pins, organized as 262,144 words by 36 bits. This synchronous SRAM integrates input registers, high speed RAM, output registers, and a one-deep write buffer	Original	PDF	CXK77P36R80GB CXK77P36R80GB -100uA IDD-37 680mA CXK77P36R80GB-33 CXK77P36R80GB-37 CXK77P36R80GB-4A
EZchip Abstract: gpon ezchip EZchip wireless Text: NP-2 20-Gigabit Network Processor with Integrated Traffic Management Product Brief EZchip’s NP-2 is a highly-flexible network processor with integrated traffic managers providing wire-speed packet processing and advanced flow-based bandwidth control. The NP-2 offers the speed of an ASIC combined with the	Original	PDF	20-Gigabit EZchip gpon ezchip EZchip wireless
CS6100 Abstract: verilog code for huffman coding jpeg encoder vhdl code huffman code generator in verilog yuv to rgb Verilog rgb yuv vhdl column-major huffman code book in verilog 2614 encoder color space converter verilog rgb ycbcr asic Text: CS6100 TM Motion JPEG Encoder Virtual Components for the Converging World The CS6100 Motion JPEG M-JPEG Encoder is a highly integrated application specific silicon core for leadingedge image compression and transmission applications. Its high performance is capable of sustaining data rates	Original	PDF	CS6100 CS6100 DS6100 verilog code for huffman coding jpeg encoder vhdl code huffman code generator in verilog yuv to rgb Verilog rgb yuv vhdl column-major huffman code book in verilog 2614 encoder color space converter verilog rgb ycbcr asic
43bh Abstract: marking code 42ae marking JC 6f diode CXK77P18E160GB CXK77P36E160GB CXK77P36E160GB-4AE CXK77P36E160GB-4E 43AF marking 43AF Text: SONY CXK77P36E160GB / CXK77P18E160GB 16Mb LW R-L HSTL High Speed Synchronous SRAMs 512K x 36 or 1M x 18 8Mb LW R-L w/ EC HSTL High Speed Synchronous SRAMs (256K x 36 or 512K x 18) 4/42/43/44 Preliminary Description The CXK77P36E160GB (organized as 524,288 words by 36 bits) and the CXK77P18E160GB (organized as 1,048,576 words	Original	PDF	CXK77P36E160GB CXK77P18E160GB CXK77P36E160GB -100uA 43bh marking code 42ae marking JC 6f diode CXK77P18E160GB CXK77P36E160GB-4AE CXK77P36E160GB-4E 43AF marking 43AF
NUC745 Abstract: NUC745ADN TSMC IO 128-PIN AC97 LQFP128 14X14X1.4 i2s PWM 32.768K Text: NUC745ADN 32-BIT ARM7TDMI-BASED MCU NUC745ADN 16/32-bit ARM microcontroller Product Data Sheet NUC745ADN Table of Contents1. GENERAL DESCRIPTION. 1 2.	Original	PDF	NUC745ADN 32-BIT 16/32-bit NUC745 NUC745ADN TSMC IO 128-PIN AC97 LQFP128 14X14X1.4 i2s PWM 32.768K

D78F0034AY Abstract: PIC16F877 stepper motor interfacing pic16f877 pwm assembly program D78F0034A instruction set of pic16f877 microcontroller advantages of microcontroller pic16f877 8051 vs pic microcontroller PIC16F887 6808 cpu D78F0034 pic16f877 pwm motor control Text: Back AMC National Semiconductor AnalogMicroController N Group COP8FLASH Agenda AMC n COP8 Architecture Overview n COP8FLASH n n n In System Programming n n n New Release: COP8SBR On-Chip Features FLASH products in development COP8FLASH ISP modes Demo of WinFLASH utility	Original	PDF	68HC908GP32 P89CE558 16-bit 10-bit D78F0034AY PIC16F877 stepper motor interfacing pic16f877 pwm assembly program D78F0034A instruction set of pic16f877 microcontroller advantages of microcontroller pic16f877 8051 vs pic microcontroller PIC16F887 6808 cpu D78F0034 pic16f877 pwm motor control
16 bit Array multiplier code in VERILOG Abstract: 8 bit Array multiplier code in VERILOG vhdl code for lvds driver i7 processor history verilog code for 128 bit AES encryption verilog code for aes encryption EP3CLS150 fpga based Numerically Controlled Oscillator freescale m9k E144 package Text: 1. Cyclone III Device Family Overview July 2012 CIII51001-2.4 CIII51001-2.4 Cyclone III device family offers a unique combination of high functionality, low power and low cost. Based on Taiwan Semiconductor Manufacturing Company TSMC low-power (LP) process technology, silicon optimizations and software	Original	PDF	CIII51001-2 16 bit Array multiplier code in VERILOG 8 bit Array multiplier code in VERILOG vhdl code for lvds driver i7 processor history verilog code for 128 bit AES encryption verilog code for aes encryption EP3CLS150 fpga based Numerically Controlled Oscillator freescale m9k E144 package
TSMC 0.18 um CMOS Abstract: 0.18-um CMOS technology characteristics Text: VariCore Embedded Programmable Gate Array Core EPGA™ 0.18 µm Family Purpose VariCore™ IP blocks are embedded, reprogrammable “soft hardware” cores designed for use in ASIC and ASSP SoC applications. The first commercially available VariCore	Original	PDF
TSMC single port sram Abstract: No abstract text available Text: SONY CXK77Q36B80AGB / CXK77Q18B80AGB 28/33/37/4 8Mb LW R-R HSTL High Speed Synchronous SRAMs 256K x 36 or 512K x 18 Preliminary Description The CXK77Q36B80AGB (organized as 262,144 words by 36 bits) and the CXK77Q18B80AGB (organized as 524,288 words by 18 bits) are high speed CMOS synchronous static RAMs with common I/O pins. These synchronous SRAMs integrate input	Original	PDF	CXK77Q36B80AGB CXK77Q18B80AGB CXK77Q36B80AGB CXK77Q18B80AGB 640mA 600mA TSMC single port sram
2f 1001 Abstract: CXK77Q18B80AGB CXK77Q36B80AGB CXK77Q36B80AGB-28 CXK77Q36B80AGB-33 sony tsmc Text: SONY CXK77Q36B80AGB / CXK77Q18B80AGB 28/33/37/4 8Mb LW LS R-R HSTL High Speed Synchronous SRAMs 256K x 36 or 512K x 18 Preliminary Description The CXK77Q36B80AGB (organized as 262,144 words by 36 bits) and the CXK77Q18B80AGB (organized as 524,288 words	Original	PDF	CXK77Q36B80AGB CXK77Q18B80AGB CXK77Q36B80AGB CXK77Q18B80AGB IDD-28 IDD-33 830mA 750mA 740mA 700mA 2f 1001 CXK77Q36B80AGB-28 CXK77Q36B80AGB-33 sony tsmc
CXK77Q18B80AGB Abstract: CXK77Q36B80AGB CXK77Q36B80AGB-28 CXK77Q36B80AGB-33 Text: SONY CXK77Q36B80AGB / CXK77Q18B80AGB 28/33/37/4 8Mb LW R-R HSTL High Speed Synchronous SRAMs 256K x 36 or 512K x 18 Preliminary Description The CXK77Q36B80AGB (organized as 262,144 words by 36 bits) and the CXK77Q18B80AGB (organized as 524,288 words by 18 bits) are high speed CMOS synchronous static RAMs with common I/O pins. These synchronous SRAMs integrate input	Original	PDF	CXK77Q36B80AGB CXK77Q18B80AGB CXK77Q36B80AGB CXK77Q18B80AGB 640mA 600mA CXK77Q36B80AGB-28 CXK77Q36B80AGB-33
0.18-um CMOS technology length and width Abstract: la 76938 TSMC 0.18 um CMOS library Jmpdma bidirectional shift register vhdl IEEE format 0.18-um CMOS technology characteristics tsmc cmos 0.18 um TSMC cmos 0.18um standard library TSMC cmos 0.18um 0.18-um SRAM Text: VariCore Embedded Programmable Gate Array Core EPGA™ 0.18µm Family Purpose VariCore™ IP blocks are embedded, reprogrammable “soft hardware” cores designed for use in ASIC and ASSP SoC applications. The first commercially available VariCore	Original	PDF
CS6100 Abstract: 1000X "Huffman coding" dynamic huffman coding Text: CS6100 Motion JPEG Encoder Virtual Components for the Converging World The CS6100 Motion JPEG M-JPEG Encoder is a highly integrated virtual component solution for leading-edge image compression and transmission applications. Its high performance is capable of sustaining data rates of	Original	PDF	CS6100 CS6100 1000X "Huffman coding" dynamic huffman coding
tsmc 130nm metal process Abstract: teradyne tiger aeroflex sram edac charactristics of cmos logic gates CCGA 472 leon3 teradyne flex tester CCGA 472 drawing 130NM cmos process parameters tsmc cmos Text: Semicustom Products UT130nHBD Hardened-by-Design HBD Standard Cell Advanced Data Sheet August 2010 www.aeroflex.com/RadHardASIC FEATURES PRODUCT DESCRIPTION Up to 15,000,000 usable equivalent gates using standard cell architecture The high-performance UT130n HBD Hardened-by-Design	Original	PDF	UT130nHBD 130nm 0x10-10 tsmc 130nm metal process teradyne tiger aeroflex sram edac charactristics of cmos logic gates CCGA 472 leon3 teradyne flex tester CCGA 472 drawing 130NM cmos process parameters tsmc cmos
SST25VF128 Abstract: SST25VF128C soic-8 200mil TSOP32 FOOTPRINT footprint WSON-8 SST12LP15A TSOP32 8 X 14 FOOTPRINT BIOS 32 Pin SST39SF040 SST25VF080B BIOS electronic clock on breadboard Text: Headquartered in Sunnyvale, California, SST designs, manufactures and markets a diversified range of memory and non-memory products for high volume applications in the digital consumer, networking, wireless communications and Internet computing markets. Leveraging its proprietary, patented SuperFlash	Original	PDF

TSMC SINGLE PORT SRAM Search Results

TSMC SINGLE PORT SRAM Result Highlights (5)

TSMC SINGLE PORT SRAM Datasheets Context Search

chn 723

AMBA AXI verilog code

TSMC cmos 0.18um

CHN 530

TSMC single port sram

CXK77P36L80GB-4A

sony tsmc

marking code 43b

7x17

CXK77P36R80GB

EZchip

CS6100

43bh

NUC745

D78F0034AY

16 bit Array multiplier code in VERILOG

TSMC 0.18 um CMOS

TSMC single port sram

2f 1001

CXK77Q18B80AGB

0.18-um CMOS technology length and width

CS6100

tsmc 130nm metal process

SST25VF128