CDCLVP2106
Abstract: QFN-40 weight
Text: CDCLVP2106 www.ti.com. SCAS887 – SEPTEMBER 2009 12 LVPECL Output, High-Performance Clock Buffer
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CDCLVP2106
SCAS887
CDCLVP2106
QFN-40 weight
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CDC337
Abstract: CDC337DBLE CDC337DW CDC337DWG4 CDC337DWR CDC337DWRG4 CDC337NS MS-013
Text: CDC337 CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS330B – DECEMBER 1990 – REVISED OCTOBER 1998 D D D D D D D DW PACKAGE TOP VIEW Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications TTL-Compatible Inputs and CMOS-Compatible Outputs
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CDC337
SCAS330B
48-mA
CDC337
CDC337DBLE
CDC337DW
CDC337DWG4
CDC337DWR
CDC337DWRG4
CDC337NS
MS-013
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SCANSTA111
Abstract: STA111
Text: SCANSTA111 Enhanced SCAN bridge Multidrop Addressable IEEE 1149.1 JTAG Port General Description The SCANSTA111 extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The advantage of a multidrop approach over a single serial scan chain is improved test throughput and the ability to remove a board
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SCANSTA111
SCANSTA111
IEEE1149
STA111
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CDC318
Abstract: No abstract text available
Text: CDC318 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS587B – JANUARY 1997 – REVISED MARCH 1998 D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps
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CDC318
18-LINE
SCAS587B
1-to-18
MIL-STD-883,
48-Pin
CDC318
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c.i 9409
Abstract: No abstract text available
Text: CDC339 CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS331 – DECEMBER 1992 – REVISED MARCH 1994 D D D D D D D DB OR DW PACKAGE TOP VIEW Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications TTL-Compatible Inputs and Outputs Distributes One Clock Input to Eight
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CDC339
SCAS331
48-mA
CLC339DBLE
CDC339DBR
CDC339DW
CDC339DWR
c.i 9409
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UT54AC
Abstract: No abstract text available
Text: Standard Products UT54ACTS899 RadHard 9-bit Latchable Transceiver with Parity Generator/Checker Datasheet March 14, 2007 www.aeroflex.com/radhard FEATURES PIN DESCRIPTION Latchable transceiver with output source/sink of 24mA Option to select generate parity and check or "feed-through"
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UT54ACTS899
28-pin
UT54AC
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SWBT13
Abstract: rta2 1553b rti
Text: UT1553B BCRT p Register-oriented architecture to enhance FEATURES p Comprehensive MIL-STD-1553B dual-redundant programmability p DMA memory interface with 64K addressability p Internal self-test p Remote terminal operations in ASD/ENASD-certified Bus Controller BC and Remote Terminal
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UT1553B
MIL-STD-1553B
MIL-STD-1773
84-pin
132-lead
84-lead
MIL-M-38510.
36-Lead
Packaging-10
SWBT13
rta2
1553b rti
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fp6160
Abstract: rta2
Text: UT1553B BCRT p Register-oriented architecture to enhance FEATURES p Comprehensive MIL-STD-1553B dual-redundant programmability p DMA memory interface with 64K addressability p Internal self-test p Remote terminal operations in ASD/ENASD-certified Bus Controller BC and Remote Terminal
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UT1553B
MIL-STD-1553B
MIL-STD-1773
84-pin
132-lead
84-lead
MIL-M-38510.
36-Lead
Packaging-10
fp6160
rta2
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Untitled
Abstract: No abstract text available
Text: CDC337 CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS330B – DECEMBER 1990 – REVISED OCTOBER 1998 D D D D D D D DW PACKAGE TOP VIEW Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications TTL-Compatible Inputs and CMOS-Compatible Outputs
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Original
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CDC337
SCAS330B
48-mA
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Untitled
Abstract: No abstract text available
Text: Standard Products UT54ACTS899 RadHard 9-bit Latchable Transceiver with Parity Generator/Checker Datasheet March, 2009 www.aeroflex.com/Logic FEATURES PIN DESCRIPTION Latchable transceiver with output source/sink of 24mA Option to select generate parity and check or "feed-through"
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UT54ACTS899
28-pin
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PDF
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Untitled
Abstract: No abstract text available
Text: CDC339 CLOCK DRIVER WITH 3ĆSTATE OUTPUTS SCAS331 − DECEMBER 1992 − REVISED MARCH 1994 D Low Output Skew, Low Pulse Skew for D D D D D D DB OR DW PACKAGE TOP VIEW Clock-Distribution and Clock-Generation Applications TTL-Compatible Inputs and Outputs
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SCAS331
CDC339
48-mA
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Untitled
Abstract: No abstract text available
Text: Product Folder Sample & Buy Support & Community Tools & Software Technical Documents CDCLVP1204 SCAS880D – AUGUST 2009 – REVISED JUNE 2014 CDCLVP1204 Four LVPECL Output, High-Performance Clock Buffer 1 Features 3 Description • • • The CDCLVP1204 is a highly versatile, low additive
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CDCLVP1204
SCAS880D
CDCLVP1204
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Untitled
Abstract: No abstract text available
Text: SN74ALS235 64 x 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY _ SQAS108A - OCTOBER 1986 - REVISED SEPTEMBER 1993 • • • • • Asynchronous Operation Organized as 64 Words by 5 Bits Data Rates From 0 to 25 MHz 3-State Outputs
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SN74ALS235
SQAS108A
300-mll
320-bit
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Untitled
Abstract: No abstract text available
Text: 3.3 V CMOS 18-BIT REGISTER 3-STATE , 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: - IDT74LVC16823A ADVANCE INFORMATION The LVC16823A18-bit edge-triggered D-type register is built using advanced dual metal CMOS technology.This high-speed, low-power register is ideal for use as a buffer register for data
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18-BIT
IDT74LVC16823A
LVC16823A18-bit
18-bit
LVC16823A
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Untitled
Abstract: No abstract text available
Text: IDT74LVCH32373A 3.3V CMOS 32-BIT ADVANCE TRANSPARENT D-TYPE LATCH INFORMATION WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD DESCRIPTION: FEATURES: - Typical tS K o (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)
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IDT74LVCH32373A
32-BIT
250ps
MIL-STD-883,
200pF,
LVCH32373A
32-bit
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Untitled
Abstract: No abstract text available
Text: IDT74FCT3807/A 3.3V CMOS 1-TO-10 CLOCK DRIVER In te g rate d D ev ice T ech n ology , Inc. FEATURES: DESCRIPTION: • 0 .5 M IC R O N C M O S Technology • G u aran teed low skew < 3 5 0 p s m ax. • V ery low duty cycle distortion < 3 5 0p s (m ax.) •
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IDT74FCT3807/A
1-TO-10
MO-150,
/13/V
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Untitled
Abstract: No abstract text available
Text: FAST CMOS BUFFER/CLOCK DRIVER IDT54/74FCT81OBT/CT Integrated Device Technology, Inc. FEATURES: • • 0.5 MICRON CM OS technology • Guaranteed low skew < 600ps max. packages Military product compliant to MIL-STD-883, Class B DESCRIPTION: • Very low duty cycle distortion < 700ps (max.)
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IDT54/74FCT81OBT/CT
600ps
MIL-STD-883,
700ps
200pF,
IDT54/74FCT81
810BT
IL-STD-883,
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Untitled
Abstract: No abstract text available
Text: 3.3V CMOS 9-BIT, 4-PORT IDT74ALVCH16409 UNIVERSAL BUS EXCHANGER ADVANCE INFORMATION WITH 3-STATE OUTPUTS AND BUS-HOLD DESCRIPTION: FEATURES: - 0.5 MICRON CMOS Technology Typical tsK o (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)
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IDT74ALVCH16409
250ps
MIL-STD-883,
200pF,
635mm
ALVCH16409
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Untitled
Abstract: No abstract text available
Text: 3.3V CMOS QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O FE A T U R E S : - 0.5 MICRON CMOS Technology - ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0 - 1,27mm pitch SOIC, 0.65mm pitch SSOP and
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MIL-STD-883,
200pF,
LVC126A:
IDT74LVC126A
2975StenderWay
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Untitled
Abstract: No abstract text available
Text: 3.3V CMOS 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS AND BUS-HOLD FEATURES: - IDT74ALVCH16836 DESCRIPTION: 0.5 MICRON CMOS Technology Typical tsK o (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)
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20-BIT
IDT74ALVCH16836
250ps
MIL-STD-883,
200pF,
635mm
20-bit
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Untitled
Abstract: No abstract text available
Text: 3.3V CMOS 16-BIT BUS T R A N S C EIV ER /R EG IS T ER WITH 3-STATE OUTPUTS, 5 VOLT TO LERAN T I/O FEA TU RES: - Typical - ESD > 2000V per MIL-STD-883, Method 3015; - 0.635mm pitch S SO P , 0.50mm pitch T S S O P tsK o (Output Skew) < 250ps > 200V using machine model (C = 200pF, R = 0)
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16-BIT
MIL-STD-883,
635mm
250ps
200pF,
IDT74LVC16646A
LVC16646A16-bit
48-Pin
56-Pin
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Untitled
Abstract: No abstract text available
Text: f e / FAST CMOS 1-TO-10 CLOCK DRIVER IDT54/74FCT807BT/CT Integrated D evice Technology, Inc. > 200V using machine model C = 200pF, R = 0 • Available in DIP, SOIC, SSOP, Cerpack and LCC packages • Military product compliant to MIL-STD-883, Class B FEATURES:
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1-TO-10
IDT54/74FCT807BT/CT
200pF,
MIL-STD-883,
250ps
350ps
100MHz
-32mA
STD-883,
IDT54/74FCT807BT/CT
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Untitled
Abstract: No abstract text available
Text: 3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O FE A T U R E S : - IDT74LVC16244A D E S C R IP TIO N : Typical tsK o (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) 0.635mm pitch SSOP, 0.50mm pitch TSSOP
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16-BIT
IDT74LVC16244A
250ps
MIL-STD-883,
200pF,
635mm
LVC16244A16-bit
LVC16244A
48-Pin
56-Pin
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Untitled
Abstract: No abstract text available
Text: IDT74LVCH16543A 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD FEATURES: - Separate latch-enable LEAB or LEBA and output-enable (OEAB or OEBA) inputs are provided for each register to per mit independent control in either direction of data flow. The Ato-B enable (CEAB) input must be low in order to enter data
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IDT74LVCH16543A
16-BIT
16-BIT
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