SCANSTA111
Abstract: STA111
Text: SCANSTA111 Enhanced SCAN bridge Multidrop Addressable IEEE 1149.1 JTAG Port General Description The SCANSTA111 extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The advantage of a multidrop approach over a single serial scan chain is improved test throughput and the ability to remove a board
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SCANSTA111
SCANSTA111
IEEE1149
STA111
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CDC318
Abstract: No abstract text available
Text: CDC318 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS587B – JANUARY 1997 – REVISED MARCH 1998 D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps
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CDC318
18-LINE
SCAS587B
1-to-18
MIL-STD-883,
48-Pin
CDC318
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bms 16s
Abstract: SWBT13 UT1553BCRTM ta306
Text: UT1553 BCRTM p Register-oriented architecture to enhance FEATURES p Comprehensive MIL-STD-1553 dual-redundant Bus p p p p p programmability p DMA memory interface with 64K addressability p Internal self-test p Radiation-hardened option available for 84-lead
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UT1553
MIL-STD-1553
MIL-STD-1773
84-lead
84-pin
84lead
MIL-M-38510.
36-Lead
Packaging-10
bms 16s
SWBT13
UT1553BCRTM
ta306
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UT54AC
Abstract: No abstract text available
Text: Standard Products UT54ACTS899 RadHard 9-bit Latchable Transceiver with Parity Generator/Checker Datasheet March 14, 2007 www.aeroflex.com/radhard FEATURES PIN DESCRIPTION Latchable transceiver with output source/sink of 24mA Option to select generate parity and check or "feed-through"
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UT54ACTS899
28-pin
UT54AC
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Untitled
Abstract: No abstract text available
Text: CDC318 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS587B – JANUARY 1997 – REVISED MARCH 1998 D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps
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CDC318
18-LINE
SCAS587B
1-to-18
MIL-STD-883,
48-Pin
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PDF
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48-PIN
Abstract: CDC318A CDC318ADL CDC318ADLG4
Text: CDC318A 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A – SEPTEMBER 1998 – REVISED JUNE 2002 D D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications
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CDC318A
18-LINE
SCAS614A
1-to-18
100-MHz
MIL-STD-883,
48-Pin
CDC318A
CDC318ADL
CDC318ADLG4
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PDF
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Untitled
Abstract: No abstract text available
Text: SCANSTA111 www.ti.com SNLS060K – AUGUST 2001 – REVISED APRIL 2013 SCANSTA111 Enhanced SCAN Bridge Multidrop Addressable IEEE 1149.1 JTAG Port Check for Samples: SCANSTA111 FEATURES DESCRIPTION • The SCANSTA111 extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The
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SCANSTA111
SNLS060K
SCANSTA111
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Untitled
Abstract: No abstract text available
Text: CDCLVD1212 www.ti.com SCAS901B – SEPTEMBER 2010 – REVISED JANUARY 2011 2:12 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD1212 FEATURES 1 • • • • • • • • • • • • 2:12 Differential Buffer Low Additive Jitter: <300 fs RMS in
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CDCLVD1212
SCAS901B
EIA/TIA-644A
40-Pin
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Untitled
Abstract: No abstract text available
Text: SCANSTA111 www.ti.com SNLS060K – AUGUST 2001 – REVISED APRIL 2013 SCANSTA111 Enhanced SCAN Bridge Multidrop Addressable IEEE 1149.1 JTAG Port Check for Samples: SCANSTA111 FEATURES DESCRIPTION • The SCANSTA111 extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The
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SCANSTA111
SNLS060K
SCANSTA111
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48-PIN
Abstract: CDC318A CDC318ADL CDC318ADLG4 CDC318ADLR
Text: CDC318A 1ĆLINE TO 18ĆLINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A − SEPTEMBER 1998 − REVISED JUNE 2002 D High-Speed, Low-Skew 1-to-18 Clock Buffer D D D D D D D D D DL PACKAGE TOP VIEW for Synchronous DRAM (SDRAM) Clock Buffering Applications
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CDC318A
18LINE
SCAS614A
1-to-18
100-MHz
MIL-STD-883,
48-Pin
CDC318A
CDC318ADL
CDC318ADLG4
CDC318ADLR
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PDF
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K3638
Abstract: 4Y04
Text: CDC318A 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A – SEPTEMBER 1998 – REVISED JUNE 2002 D D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications
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Original
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CDC318A
18-LINE
SCAS614A
1-to-18
100-MHz
MIL-STD-883,
48-Pin
K3638
4Y04
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PDF
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Untitled
Abstract: No abstract text available
Text: FAST CMOS BUFFER/CLOCK DRIVER IDT49FCT3805/A Integrated Device Technology, Inc. FEATURES: DESCRIPTION: 0 .5 M IC R O N C M O S Technology T h e F C T 3 8 0 5 /A is a 3 .3 volt, non-inverting clock driver built G u aranteed low skew < 500p s m ax. using advanced dual m etal C M O S technology. T h e device
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IDT49FCT3805/A
IL-STD-883,
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Untitled
Abstract: No abstract text available
Text: IDT74FCT3807/A 3.3V CMOS 1-TO-10 CLOCK DRIVER In te g rate d D ev ice T ech n ology , Inc. FEATURES: DESCRIPTION: • 0 .5 M IC R O N C M O S Technology • G u aran teed low skew < 3 5 0 p s m ax. • V ery low duty cycle distortion < 3 5 0p s (m ax.) •
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IDT74FCT3807/A
1-TO-10
MO-150,
/13/V
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Untitled
Abstract: No abstract text available
Text: IDT49FCT805BT/CT IDT49FCT806BT/CT FAST CMOS BUFFER/CLOCK DRIVER Integrated Device Technology, Inc. FEATURES: Military product compliant to MIL-STD-883, Class B • » • • • • • • • • • 0.5 MICRON CMOS Technology Guaranteed low skew < 500ps max.
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IDT49FCT805BT/CT
IDT49FCT806BT/CT
MIL-STD-883,
500ps
600ps
-32mA
200pF,
IDT49FCT805B
IDT49FCT805BT/CT,
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Untitled
Abstract: No abstract text available
Text: IDT74LVC843A 3.3V CMOS 9-BIT ADVANCE INFORMATION BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O relatively low-impedance loads. The device is particularly suit able for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The nine latches are trans
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IDT74LVC843A
MIL-STD-883,
200pF,
635mm
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80c85
Abstract: HS80C85
Text: S H S - 5 4 C 1 3 8 R H R a d ia t io n H a r d e n e d February 1996 3 - L in e to 8 - L in e D e c o d e r /D e m u lt ip le x e r Features Pinouts • Devices QML Qualified in Accordance With MIL-PRF-38535 16 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE SBDIP
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MIL-PRF-38535
IL-STD-1835
CDIP2-T16
HS-54C
0b573D
80c85
HS80C85
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LVC139A
Abstract: DSC-4720
Text: IDT74LVC139A 3.3V CMOS DUAL ADVANCE INFORMATION 2-LINE TO 4-LINE DECODER/DEMULTIPLEXER, 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: - 0.5 M IC R O N C M O S T e c h n o lo g y ESD > 2 0 0 0 V p e r M IL -S T D -8 8 3 , M e th o d 3 0 1 5 ; > 2 0 0 V using m a c h in e m o d e l C = 2 0 0 p F , R = 0
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IDT74LVC139A
tPLH11
tPHL11
LVC139A
DSC-4720
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Untitled
Abstract: No abstract text available
Text: jd t In te g ra te d D e v ic e T e c h n o lo g y , l i e . 3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O IDT74LVC16646A DESCRIPTION: FEATURES: The LVC16646A 16-bit bus transceiver/register is built us ing advanced dual metal CMOS technology. This high-speed,
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16-BIT
IDT74LVC16646A
250ps
MIL-STD-883,
200pF,
635mm
LVC16646A:
tPHL11
IDT74LVC16646A
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Untitled
Abstract: No abstract text available
Text: 3.3V CMOS 1-TO-10 CLOCK DRIVER IDT74FCT3807/A Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • • • • • • • • • • • • • The FCT3807/A 3.3V clock driver is built using advanced dual metal CMOS technology. This low skew clock driver
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1-TO-10
IDT74FCT3807/A
350ps
FCT3807/A
IDT74FCT3807/A
IDT74FCT
S020-2)
S020-7)
S020-8)
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Untitled
Abstract: No abstract text available
Text: 3.3V CMOS OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O IDT74LVCR2245A ADVANCE INFORMATION DESCRIPTION: FEATURES: - 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0 - 1,27mm pitch SOIC, 0.65mm pitch SSOP,
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OCR Scan
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MIL-STD-883,
200pF,
635mm
LVCR2245A:
IDT74LVCR2245A
LVCR2245A
R2245A
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sidd
Abstract: SA2995 Harris top marking
Text: 33 fcKHffiSR HS-54C138RH Radiation Hardened 3-Line to 8-Line Decoder/Demultiplexer December 1992 Pinouts Features 16 PIN DIP CASE OUTLINE D2, CONFIGURATION 3 TOP VIEW • Radiation Hardened EPI-CMOS - Total Dose 1 x 10s RAD Si - Latch-Up Immune > 1 x 1012 RAD(Si)/s
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HS-54C138RH
SA2995
80C85RH
HS-54C138RH
sidd
SA2995
Harris top marking
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S5807
Abstract: No abstract text available
Text: Ö Qu ality S em iconducto r , I n c . Guaranteed Low Skew CMOS Clock Driver/Buffer QS5807 QS52807 FEATURES/BENEFITS DESCRIPTION • 10 outputs • Rail-to-rail output voltage swing • 25Q on-chip resistors available for low noise • Input hysteresis for better noise margin
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QS5807
QS52807
S5807
tpHL11
tpLH11
MDSC-00024-01
QS5807,
QS52807AQ
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Untitled
Abstract: No abstract text available
Text: IDT54/74F CT3807/A PRELIMINARY 3.3V CMOS I-TO -IO CLOCK DRIVER Integrated Device Technology, Inc. FEATURES: Available in DIP, SOIC, SSOP, QSOP, Cerpack and LCC packages Military product compliant to MIL-STD-883, Class B 0.5 MICRON CMOS Technology Guaranteed low skew < 350ps max.
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IDT54/74F
CT3807/A
MIL-STD-883,
350ps
FCT3807/A
This046
4A25771
IDT54/74FCT3807/A
1-TO-10
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PDF
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Untitled
Abstract: No abstract text available
Text: HS-54C138RH S em iconductor Radiation Hardened 3-Line to 8-Line Decoder/Demultiplexer February 1996 Pinouts Features • Devices QML Qualified in Accordance With MIL-PRF-38535 16 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE SBDIP MIL-STD-1835 CDIP2-T16 • Detailed Electrical and Screening Requirements are
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OCR Scan
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HS-54C138RH
MIL-PRF-38535
MIL-STD-1835
CDIP2-T16
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PDF
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