Untitled
Abstract: No abstract text available
Text: V73CAG01808RA HIGH PERFORMANCE 1Gbit DDR3 SDRAM 8 BANKS X 16Mbit X 8 - - - - I9 DDR3-1066 DDR3-1333 2.5 ns 2.5 ns Clock Cycle Time tCK7, CWL=6 1.875 ns 1.875 ns Clock Cycle Time ( tCK8, CWL=6 ) 1.875 ns 1.875 ns Clock Cycle Time ( tCK9, CWL=7 ) - 1.5 ns
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Original
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V73CAG01808RA
16Mbit
DDR3-1066
tCK10,
DDR3-1333
78-ball
1333Mbps/1066Mbps
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PDF
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J32CG
Abstract: 61a3 mosfet BCM5461KFB 61a3 58A6 bcm5461 60F10 L32SD DQ27152 A26B4
Text: 1 2 4 3 5 6 7 TABLE OF CONTENTS F F PAGE 02 - BLOCK DIAGRAM PAGE 03 - 750GX ADDRESS/DATA BUSSES PAGE 04 - 750GX CONTROLS AND GROUND PAGE 05 - 750GX POWER AND DECOUPLING PAGE 06 - TSI108 PROCESSOR BUS INTERFACE PAGE 07 - TSI108 MEMORY INTERFACE PAGE 08 - DDR2 DIMM CONNECTOR SLOT 0
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Original
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750GX
TSI108
RS232
NC7SZ00
J32CG
61a3 mosfet
BCM5461KFB
61a3
58A6
bcm5461
60F10
L32SD
DQ27152
A26B4
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PDF
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Untitled
Abstract: No abstract text available
Text: PRELIMINARY V73CBG04168RA HIGH PERFORMANCE 4Gbit DDR3L SDRAM 8 BANKS X 32Mbit X 16 - G6 - H7 - I9 - J11 - K13 DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 Clock Cycle Time tCK5, CWL=5 3.0ns 3.0ns 3.0ns 3.0ns 3.0ns Clock Cycle Time ( tCK6, CWL=5 ) 2.5ns
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Original
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V73CBG04168RA
32Mbit
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
DDR3-1866
tCK10,
tCK11,
V73CBG04168RA
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PDF
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G0240
Abstract: No abstract text available
Text: PRELIMINARY V73CAG02808RA HIGH PERFORMANCE 2Gbit DDR3 SDRAM 8 BANKS X 32Mbit X 8 - G6 - H7 - I9 - J11 DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Clock Cycle Time tCK5, CWL=5 3.0ns 3.0ns 3.0ns 3.0ns Clock Cycle Time ( tCK6, CWL=5 ) 2.5ns 2.5ns 2.5 ns 2.5 ns
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Original
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V73CAG02808RA
32Mbit
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
tCK10,
tCK11,
V73CAG02808RA
G0240
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PDF
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250M
Abstract: ADSP-TS101S BR70 TigerSHARC DSP Instruction set specification
Text: T a DSP Microcomputer ADSP-TS101S KEY FEATURES 250 MHz, 4.0 ns Instruction Cycle Rate 6M Bits of Internal—On-Chip—SRAM Memory 19 ؋ 19 mm 484-Ball or 27 ؋ 27 mm (625-Ball) PBGA Package Dual Computation Blocks—Each Containing an ALU, a Multiplier, a Shifter, and a Register File
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Original
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ADSP-TS101S
484-Ball)
625-Ball)
ADSP-TS101SAB1-000
ADSP-TS101SAB2-000
B-625
B-484
250M
ADSP-TS101S
BR70
TigerSHARC DSP Instruction set specification
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PDF
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Untitled
Abstract: No abstract text available
Text: PRELIMINARY V73CBG01 808/168 RB HIGH PERFORMANCE 1Gbit DDR3L SDRAM 8 BANKS X 16Mbit X 8 8 BANKS X 8Mbit X 16 - G6 - H7 - I9 - J11 - K13 DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 Clock Cycle Time ( tCK5, CWL=5 ) 3.0ns 3.0ns 3.0ns 3.0ns 3.0ns Clock Cycle Time ( tCK6, CWL=5 )
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Original
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V73CBG01
16Mbit
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
DDR3-1866
tCK10,
tCK11,
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PDF
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Untitled
Abstract: No abstract text available
Text: PRELIMINARY V73CAG01 808/168 RB HIGH PERFORMANCE 1Gbit DDR3 SDRAM 8 BANKS X 16Mbit X 8 8 BANKS X 8Mbit X 16 - G6 - H7 - I9 - J11 - K13 DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 Clock Cycle Time ( tCK5, CWL=5 ) 3.0ns 3.0ns 3.0ns 3.0ns 3.0ns Clock Cycle Time ( tCK6, CWL=5 )
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Original
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V73CAG01
16Mbit
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
DDR3-1866
tCK10,
tCK11,
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PDF
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TCK9004
Abstract: T306F tvga 386SX chipset 640x400 el display Tvga9200cxr 0636 FL AA8M vl-bus 486DX symphony chip set motherboard
Text: T V G A 9 2 0 0 C X r PRELIMINARY DATASHEET TVGA9200CXr SUPER VGA CONTROLLER Features Benefits • Single-chip solution for IBM PC/AT 32-bit VESA Local Bus VL-Bus ■ Provides a versatile and high-performance solution. Compatibility with the VL-Bus standard provides a
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OCR Scan
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TVGA9200CXr
32-bit
24-bit
512Kx8
256Kx4
16-bit
80/132-colum
TCK9004
T306F
tvga
386SX chipset
640x400 el display
0636 FL
AA8M
vl-bus
486DX symphony chip set motherboard
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PDF
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tvga8900
Abstract: TVGA8900C TCK9004 TVGA8900D tvga8900cl trident TVGA8900C TKD8001 Tvga TVGA-8900 trident micro
Text: TRID EN T M I C R O S Y S T E M S INC b?E » Mi 'iGOeiöe □ □ G G 2 2 Iî TT4 • TRIS TVGA8900D SUPER VGA CONTROLLER Overview ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ General Description Single-chip solution for IBM PC/AT and compatible,
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OCR Scan
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TVGA8900D
16-bit
256Kx4,
256Kx8,
256Kxl6,
512Kx4
512Kx8
256Kx4
640x400
640x480
tvga8900
TVGA8900C
TCK9004
tvga8900cl
trident TVGA8900C
TKD8001
Tvga
TVGA-8900
trident micro
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PDF
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M 50556
Abstract: 50556 act mx hf nu
Text: [Ordering number : EN5055A ~| CMOS LSI No. 5055A SAXYO L C 3 8 2 1 6 1 T - 1 7 2 MEG 65536 words x 16 bits x 2 banks Synchronous DRAM Overview Package Dimensions The LC382I61T is a 3.3 V single-voltage power supply unit: mm synchronous D RAM s with a 65536-word x 16-bii x 2-
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OCR Scan
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LC382161T-17
LC382I61T
65536-word
16-bii
LC382161T
50-pin
M 50556
50556
act mx hf nu
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PDF
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74HTC244
Abstract: TCK9002 TCK9004 640X400 Stn 640x200 mono 3c509 Tvga 386SX chipset Hsync Vsync RGB LCD laptop TVGA9100B
Text: T R I D EN T M I C R O S Y S T E M S INC blE » • ^ 0 0 2 1 0 2 OOOÜG'i? bñ3 « T R I D // T L C D 9 1 0 0 B P R E L I M I N A R Y D A T A SHEET Ii — -S Z L -3 3 -4 5 * / Trident TLCD9100B LCD/CRT CONTROLLER Benefits Features Single-chip solution for IBM PC/AT and compatible,
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OCR Scan
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TLCD9100B
16-bit
640x480
65BSC
PFP160
74HTC244
TCK9002
TCK9004
640X400
Stn 640x200 mono
3c509
Tvga
386SX chipset
Hsync Vsync RGB LCD laptop
TVGA9100B
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PDF
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TC59WM807BFT
Abstract: No abstract text available
Text: TOSHIBA THMD51E20B70,75,80 TENTATIVE TOSHIBA HYBRID DIGITAL INTEGRATED CIRCUIT 67,108,864-WORD BY 72-BIT DDR SYNCHRONOUS DRAM MODULE DESCRIPTION The THMD51E20B is a 67,108,864-word by 72-bit Double Data Rate synchronous dynamic RAM module consisting of 18 TC59WM807BFT DRAMs and PLL/Registers on a printed circuit board.
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OCR Scan
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THMD51
E20B70
864-WORD
72-BIT
THMD51E20B
TC59WM807BFT
72-bit
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PDF
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V11J
Abstract: ba7k 500C LC382161T-17
Text: [Ordering number : EN5055A ~| CMOS LSI No. 5055A SAXYO L C 3 8 2 1 6 1 T - 1 7 2 MEG 65536 words x 16 bits x 2 banks Synchronous DRAM Overview Package Dimensions The LC382I61T is a 3.3 V single-voltage power supply unit: mm synchronous D RAM s with a 65536-word x 16-bii x 2-
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OCR Scan
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LC382161T-17
LC382I61T
65536-word
16-bit
LC382161T
50-pin
V11J
ba7k
500C
LC382161T-17
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PDF
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TC59WM803BFT
Abstract: THMD1GE2SB70
Text: TOSHIBA THMD1GE2SB70,75,80 TENTATIVE TO SHIBA HYBRID DIGITAL INTEGRATED CIRCUIT 134,217,728-WORD BY 72-BIT DDR SYNCHRONOUS DRAM MODULE DESCRIPTION The THMD1GE2SB is a 134,217,728-word by 72-bit Double Data Rate synchronous dynamic RAM module consisting of 36 TC59WM803BFT DRAMs and PLL/Registers on a printed circuit board.
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OCR Scan
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THMD1GE2SB70
728-WORD
72-BIT
TC59WM803BFT
72-bit
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PDF
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