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    Abstract: No abstract text available
    Text: CTSLVEL16VR PECL/ECL Oscillator Gain Stage & Buffer with Selectable Enable MLP8, MLP16 Features      Block Diagram Minimizes External Components Selectable Enable Polarity and Threshold CMOS or PECL High Bandwidth for 1GHz Similar Operation as CTS100EL16


    Original     		PDF CTSLVEL16VR MLP16 CTS100EL16 CTSLVEL16VR CTSLVEL16VRNNG CTSLVEL16VRNLG RevB0114