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    Text: Renesas LSIs M5M5V5636GP –16I,13I Preliminary Notice: This is not final specification. Some parametric limits are subject to change. 18874368-BIT 524288-WORD BY 36-BIT NETWORK SRAM DESCRIPTION APPLICATION The M5M5V5636GP is a family of 18M bit synchronous SRAMs


    Original     		PDF M5M5V5636GP 18874368-BIT 524288-WORD 36-BIT) M5M5V5636GP 524288-words 36-bit. REJ03C0076