U112
Abstract: CONTACTOR
Text: LOGIC LMU112 D E V IC E S INCORPORATED 12 x 12-bit Parallel Multiplier FEATURES □ 50 ns W orst-C ase M ultiply Tim e □ Low Pow er C M O S T echnology □ R eplaces TR W M PY112K _1 T w o's C om plem ent or U nsigned O perands □ T hree-State O utputs
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LMU112
12-bit
PY112K
LMU112PC60
LMU112PC50
LMU112DC60
LMU112DC50
LMU112JC60
LMU112JC50
U112
CONTACTOR
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B1016
Abstract: LMU11250
Text: LMU112 12 x 12-bit Parallel Multiplier □ FV IC E S IN C O R P Q R A T F D FEATURES □ 25 ns W orst-Case M ultiply Time □ Low Power CMOS Technology □ Replaces Fairchild M PY112K □ Tw o's Complement or Unsigned Operands □ Three-State Outputs □ Package Styles Available:
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LMU112
12-bit
LMU112
MPY112K.
LMU112JC50
LMU112JC25
LMU112PC50
LMU112PC25
B1016
LMU11250
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Untitled
Abstract: No abstract text available
Text: LMU112 12 x 12-bit Parallel Multiplier D E V IC E S IN C O R P O R A T E D DESCRIPTION FEATURES □ 25 ns W orst-Case M ultiply Time □ Low Power CMOS Technology □ Replaces Fairchild M PY112K □ Tw o's Complement or Unsigned Operands □ Three-State Outputs
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LMU112
12-bit
PY112K
48-pin
52-pin
LMU112
MPY112K.
LMU112JC50
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Untitled
Abstract: No abstract text available
Text: . o <13 »nil CI» LMU112 12 x 12-bit Parallel M ultip lie r T he L M U 112 is a high-speed, low p ow er 12-bit parallel m ultiplier bu ilt using ad vanced C M O S technology. The L M U 112 is pin and functionally com patible w ith T R W 's M PY112K . □ 25 ns W orst-C ase M u ltiply Tim e
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48-pin
52-pin
LMU112
12-bit
PY112K
LMU112JC60
LMU112JC50
LMU112JC25
LMU112PC60
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Untitled
Abstract: No abstract text available
Text: I M l 1119 - i; r LMU112 , 12 x 12-bit Parallel Multiplier DEVICES INCORPORATED FEATURES_ _ □ 25 ns W orst-Case M ultiply Time □ Low Power CMOS Technology □ Replaces TRW M PY112K □ Tw o's Complement or Unsigned Operands □ Three-State Outputs
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LMU112
12-bit
PY112K
MIL-STD-883,
48-pin
52-pin
LMU112
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Untitled
Abstract: No abstract text available
Text: LMU112 12 x 12-bit Parallel Multiplier DESCRIPTION FEATURES □ 50 ns W orst-C ase M u ltiply Tim e T h e L M U 112 is a high-speed, low pow er 12-bit parallel m ultiplier built using advanced C M O S technology. T he LM U 112 is pin and functionally com patible w ith T R W 's M PY112K .
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LMU112
12-bit
PY112K
LMU112DC60
LMU112DC50
LMU112JC60
LMU112JC50
LMU112PC60
LMU112PC50
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Trw 112k
Abstract: No abstract text available
Text: 12 x 12-bit FEATURES DESCRIPTION □ 50 n s W o rst-C a se M u ltip ly T im e T h e LM U 112 is a h ig h -sp eed , lo w p o w e r, 12-bit p arallel m u ltip lier b u ilt u sin g a d v a n c e d C M O S tech n ology. T h e L M U 1 12 is p in a n d fu n ctio n ally
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12-bit
12-bit
PY112K
LMU112
Trw 112k
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K3467
Abstract: TRW 012HJ1C MPY008H tdc1008 smd marking g8 smd Pl9 012hj TMC216H MPY012H 012HJ1C
Text: TjRSnf F ix e d -P o in t A rith m e tic Description Product TM C208K-1 Size Clock Rate 1 MHz P o w e r1 (Watts) Grades2 Package Notes Page M u ltip lier 8x8 45 50 65 70 0.55 0.55 0.55 0.55 85, N5 B5 65, N5 B5 40 40 40 40 Pin Pin Pin Pin DIP DIP DIP DIP
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TMC208K-1
MPY008H.
TMC28KU-1
MPY012H
12x12
24-Bit
MPY112K
16-Bit
K3467
TRW 012HJ1C
MPY008H
tdc1008
smd marking g8
smd Pl9
012hj
TMC216H
012HJ1C
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MPY112K
Abstract: No abstract text available
Text: PY112K Multiplier 1 2 x 1 2 Bit, 50ns The PY112K is a video-speed 1 2 x 1 2 bit parallel m ultiplier w h ich operates at a 50ns cycle tim e 20M H z m ultiplication rate . The m ultiplicand and th e m ultiplier may be specified to g e th e r as tw o 's com plem ent or
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MPY112K
MPY112K
16-bit
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