Untitled
Abstract: No abstract text available
Text: 54AC11109, 74AC11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET TI0066— D2957, M ARCH 1987— REVISED M ARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11109 . . . J PACKAGE 74AC11109 . . . D OR N PACKAGE TOP VIEW
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54AC11109,
74AC11109
TI0066--
D2957,
500-mA
STD-883C
300-mil
54AC11109
74AC11109
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SN74HC74
Abstract: No abstract text available
Text: SN54HC74, SN74HC74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET _ SCLS094A - DECEMBER 1982 - REVISED JANUARY 1996 Package Options Include Plastic Small-Outline D , Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and
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SN54HC74,
SN74HC74
SCLS094A
300-mil
SN54HC74.
SN74HC74
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Untitled
Abstract: No abstract text available
Text: SN5409, SN54LS09, SN54S09, SN7409, SN74LS09, SN74S09 QUADRUPLE 2-INPUT POSITIVE-AND GATES WITH OPEN-COLLECTOR OUTPUTS DECEMBER 1 9 8 3 -R E V IS E D M A R C H 1 9 8 8 Package Options Include Plastic "Sm all Outline" P ackages, Ceram ic Chip Carriers and Flat P ackages, and Plastic and Ceram ic
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SN5409,
SN54LS09,
SN54S09,
SN7409,
SN74LS09,
SN74S09
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Untitled
Abstract: No abstract text available
Text: 54AC11032, 74AC11032 QUADRUPLE 2-INPUT POSITIVE-OR GATES TI0060— D2957, JULY 1987— REVISED MARCH 1990 54A C 11032 . . . J PACKAGE 74A C 11032 . . . D OR N PACKAGE • Flow-Through Architecture to Optimize PCB Layout TOP VIEW • Center-Pin V c c and GND Configurations to
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54AC11032,
74AC11032
TI0060--
D2957,
500-mA
300-mil
54AC11032
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sn 74 ls 11 020 n
Abstract: LS1020A LS102
Text: SN 54A LS1020A , S N 74 A LS 1 020 A DUAL 4-INPUT POSITIVE-NAND BUFFERS D2661, APRIL 1982-REVISED MAY 1986 • Buffer Version of 'A LS20B • Package Options Include Plastic "Sm all Outline" Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-m il
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LS1020A
D2661,
1982-REVISED
LS20B
300-m
LS1020A
SN74ALS1
SN74ALS1020A
LS102
sn 74 ls 11 020 n
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Untitled
Abstract: No abstract text available
Text: 54AC11021,74AC11021 DUAL 4-INPUT POSITIVE-AND GATES _ D2957. JULY 1987 - REVISED APRIL 1993 54AC11021 . . . J PACKAGE 74AC11021 . . . D OR N PACKAGE TOP VIEW * Flow-Through Architecture Optimizes PCB Layout * Center-Pin Vcc and GND Configurations
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54AC11021
74AC11021
D2957.
500-mA
300-mll
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Untitled
Abstract: No abstract text available
Text: 54AC11002, 74AC11002 QUADRUPLE 2-INPUT POSITIVE-NOR GATES D2957, JUNE 1987 - REVISED APRIL 1993 54AC11002 . . . J PACKAGE 74AC11002 . . . D OR N PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout Center-Pin Vcc and GND Configuration Minimizes High-Speed Switching Noise
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54AC11002,
74AC11002
D2957,
500-mA
300-mil
54AC11002
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IC SN74HC
Abstract: SN74HCTOO SN74HC
Text: SN54HCT00, SN74HCT00 QUADRUPLE 2-INPUT POSITIVE NANO GATES D 3 2 4 3 , NOVEMBER 1968 Inputs are TTL-Voftage Compatible S N 54H C T00 S N 74H C T00 Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil
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SN54HCT00,
SN74HCT00
300-mil
74Herating
SN54HC
SN74HC
IC SN74HC
SN74HCTOO
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marking 3G
Abstract: No abstract text available
Text: TC4S01F TO SHIBA C MOS DIGITAL INTEGRATED C IR C U IT SILICO N M ONOLITHIC 2 INPUT NOR GATE Unit in mm + 0.2 23-0.3 The TC4S01F is 2-input positive logic NOR gates. + 0.2 Gate output w ith in v e rte r buffer im proves the 16 input-output ch arac te ristic s and if th e load
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TC4S01F
TC4S01F
Ta-25
marking 3G
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Untitled
Abstract: No abstract text available
Text: TOSHIBA TC4S11F TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC4S11F 2 INPUT N A N D GATE The TC4S11F is 2-input positive logic NAND gates. Gate output with inverter buffer improve the inputoutput characteristics and even if the load capacitance
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TC4S11F
TC4S11F
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74als1010
Abstract: 74ALS1010A 54als1010
Text: TYPES SN54ALS1010A, SN74ALS1010A TRIPLE 3-INPUT POSITIVE-NAND BUFFERS 0 2 6 6 1 , A P R IL 1 9 8 2 — R E V IS E D D E C E M B E R 1 9 8 3 Buffer Version o f 'A L S 1 0 SN 54 A LS 1 0 1 0 A . . . J PACKAGE Package O ptions Include Both Plastic and Ceram ic C h ip Carriers in Addition to Plastic
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SN54ALS1010A,
SN74ALS1010A
74ALS1010A
74als1010
54als1010
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logic diagram of 7432
Abstract: Texas Instruments TTL 7432
Text: SN5432, SN 54LS32, SN54S32. SN7432, SN74LS32, SN74S32 QUADRUPLE 2-INPUT POSITIVE-OR GATES DECEMBER 1983-REVISED MARCH 1988 Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs • SN 5432. SN 54LS32, SN 54S 32 . . . J OR W PACKAGE
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SN5432,
54LS32,
SN54S32.
SN7432,
SN74LS32,
SN74S32
1983-REVISED
SN54LS32
logic diagram of 7432
Texas Instruments TTL 7432
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74ALS8003
Abstract: No abstract text available
Text: TYPES SN54ALS8003, SN74ALS8003 DUAL 2-INPUT POSITIVE-NAND GATES D 2 7 4 6 . JU LY 1 9 8 3 -R E V IS E D DECEMBER 1 9 8 3 • Package Options Include Both Plastic and Ceramic Chip Carriers in Addition to Plastic and Ceramic DIPs. S N 54A LS 8003 . . . JG PACKAGE
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SN54ALS8003,
SN74ALS8003
LS8003
74ALS8003
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Untitled
Abstract: No abstract text available
Text: SN54LS15, SN54S15, SN74LS15, SN74S15 TRIPLE 3 INPUT POSITIVE AND GATES WITH OPEN-COLLECTOR OUTPUTS A P R IL 1 9 8 5 — R E V IS E D M A R C H Package Options Include Plastic "Sm all Outline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic
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SN54LS15,
SN54S15,
SN74LS15,
SN74S15
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Untitled
Abstract: No abstract text available
Text: SN54HC132, SN74HC132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS SCLS034B - DECEMBER 1982 - REVISED JANUARY 1996 • • • • • Operation From Very Slow Input Transitions Temperature-Compensated Threshold Levels High Noise Immunity Same Pinouts as ’HCOO
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SN54HC132,
SN74HC132
SCLS034B
300-mll
SN54HC132
SN74HC132
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Untitled
Abstract: No abstract text available
Text: 54ACT11002,74ACT11002 QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCAS003A - D2957, JUNE 1987 - REVISED APRIL 1993 Inputs Are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout Center-PIn V^c and GND Configurations Minimize High-Speed Switching Noise
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54ACT11002
74ACT11002
SCAS003A
D2957,
500-mA
300-mll
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Untitled
Abstract: No abstract text available
Text: SN54ALS11A, SN54AS11, SN74ALS11A, SN74AS11 TRIPLE 3-INPUT POSITIVE-AND GATES SDAS009C - MARCH 1984 - REVISED DECEMBER 1994 • Package Options Include Plastic Small-Outline D Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
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SN54ALS11A,
SN54AS11,
SN74ALS11A,
SN74AS11
SDAS009C
300-mil
SN54AS11
SNS4ALS11
SN54AS11
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S1912
Abstract: las19u
Text: INTEGRATED CIRCU ITS U N IT R O D E 5 AMP POSITIVE VOLTAGE REGULATORS LAS 1900 SERIES FEATURES DESCRIPTION • Guaranteed Power Dissipation 50 Watts fa 80°C Case • Guaranteed input-output differential: - 2.6 Volts • Low noise, band gap reference • Remote sense capability
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O-247
S1912
las19u
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L78015
Abstract: No abstract text available
Text: TL780 SERIES POSITIVE VOLTAGE REGULATORS SLVS055B - APRIL 1981 - REVISED AUGUST 1995 • ±1% Output Tolerance at 25°C • +2% Output Tolerance Over Full Operating Range • Thermal Shutdown • Internal Short-Circuit Current Limiting • Pinout Identical to |jA7800 Series
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TL780
SLVS055B
jA7800
iA7800
1N4001
TL780-XX
L78015
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Untitled
Abstract: No abstract text available
Text: S IM 54ALS1 0 1 0A , SIM 74ALS1 □ 1 0 A TRIPLE 3 INPUT POSITIVE N A N D B U FFE R S D 2 6 6 1 , A P R IL 1 9 8 2 • Buffer Version of 'A LS 10A • Package Outline” Addition Ceramic S N 74A LS 1010A . . . D O R N • -R E V IS E D M A Y 1 9 8 6 S N 5 4 A L S 1 0 1 0 A . . . J PACKAGE
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54ALS1
74ALS1
300-m
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LT1036CKV
Abstract: 4-lead to-3
Text: LT1036M, LT1036C LOGIC CONTROLLED POSITIVE REGULATORS 0 3 2 1 9 , JU L Y 1 9 8 8 -R E V IS E D JA N U A R Y 1989 Two Regulated Outputs + 12 V at 3 A + 5 V at 75 mA • 2% Output Voltage Tolerance • 60-dB Ripple Rejection KJ PACKAGE TOP VIEW GND (CASE]
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LT1036M,
LT1036C
60-dB
LT1036CKV
4-lead to-3
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74as32
Abstract: No abstract text available
Text: SN54ALS32, SN54AS32, SN74ALS32, SN74AS32 QUADRUPLE 2-INPUT POSITIVE-OR GATES D 2 6 6 1 , A P R IL 1 9 8 2 - R E V I S E D M A Y 1 9 8 6 • Package Options Include Plastic "Sm all Outline" Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-m il
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SN54ALS32,
SN54AS32,
SN74ALS32,
SN74AS32
300-m
74as32
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Untitled
Abstract: No abstract text available
Text: TC4S71F TOSHIBA C MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 2 INPUT OR GATE Unit in nm The TC4S71F contains 2-input positive logic O R gates. + 0.2 1.6-5.1 Gate output with inverter buffer improves the input-output ch aracteristics and if the load
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TC4S71F
TC4S71F
Ta-25
C/10sec.
CL-50pF)
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74as74
Abstract: No abstract text available
Text: SN74ALS74A, SN74AS74, SN54ALS74A, SN54AS74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET D 2M 1, APRIL 1982 - REVISED SEPTEM BER 1987 Package Options Includa Plaatlc "Sm a ll OutHna" Package!, Ceramlc Chip Carrlara. and Standard Plattlc and Caramic 300-mll
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SN74ALS74A,
SN74AS74,
SN54ALS74A,
SN54AS74
300-mll
8NS4ALS74A.
SN74ALS74A.
8N64AS74A
74AS74A
74as74
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