PECL 554 Search Results

PECL 554 Result Highlights (5)

Part	Manufacturer	Description
508MILFT	Renesas Electronics Corporation	PECL to CMOS Converter
507M-01LF	Renesas Electronics Corporation	PECL Clock Synthesizer
507M-01LFT	Renesas Electronics Corporation	PECL Clock Synthesizer
507M-01ILF	Renesas Electronics Corporation	PECL Clock Synthesizer
508MLF	Renesas Electronics Corporation	PECL to CMOS Converter

PECL 554 Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
ICS553 Abstract: ICS552-02 ICS554-01 ICS554G-01I ICS554G-01IT MAN09 Text: ICS554-01 LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT Description Features The ICS554-01 is a low skew clock buffer with a single complimentary PECL input to four PECL outputs. Part of ICS’ Clock BlocksTM family, this is our lowest skew PECL clock buffer. For parts which do not require PECL	Original	ICS554-01 ICS554-01 ICS553 ICS552-02 MK74CBxxx 200MHz ICS554G-01I ICS554G-01IT MAN09	PDF
ICS554-01 Abstract: ICS552-02 ICS553 ICS554G-01 ICS554G-01T MAN09 Text: ICS554-01 LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT Description Features The ICS554-01 is a low skew clock buffer with a single complimentary PECL input to four PECL outputs. Part of ICS’ Clock BlocksTM family, this is our lowest skew PECL clock buffer. For parts which do not require PECL	Original	ICS554-01 ICS554-01 ICS553 ICS552-02 MK74CBxxx 200MHz ICS554G-01 ICS554G-01T MAN09	PDF
Untitled Abstract: No abstract text available Text: DATA SHEET ICS554-01A ICS554-01A LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUTLOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT Description Features The ICS554-01A is a low skew clock buffer with a single complimentary PECL input to four PECL outputs. Part of ICS’ Clock BlocksTM family, this is our	Original	ICS554-01A ICS554-01, ICS553 ICS552-02 MK74CBxxx 199707558G	PDF
Untitled Abstract: No abstract text available Text: DATASHEET ICS554-01A LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT Description Features The ICS554-01A is a low skew clock buffer with a single complimentary PECL input to four PECL outputs. Part of ICS’ Clock BlocksTM family, this is our lowest skew PECL	Original	ICS554-01A ICS554-01, ICS553 ICS552-02 MK74CBxxx 199707558G	PDF
ICS552-02 Abstract: ICS553 ICS554-01 ICS554-01A 554G-01AILF Text: DATASHEET ICS554-01A LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT Description Features The ICS554-01A is a low skew clock buffer with a single complimentary PECL input to four PECL outputs. Part of IDT’s Clock BlocksTM family, this is our lowest skew PECL	Original	ICS554-01A ICS554-01A ICS554-01, ICS553 ICS552-02 MK74CBxxx ICS554-01 554G-01AILF	PDF
Untitled Abstract: No abstract text available Text: DATASHEET ICS554-01A LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT Description Features The ICS554-01A is a low skew clock buffer with a single complimentary PECL input to four PECL outputs. Part of ICS’ Clock BlocksTM family, this is our lowest skew PECL	Original	ICS554-01A ICS554-01, ICS553 ICS552-02 MK74CBxxx 199707558G	PDF
ics554 clock buffer Abstract: ICS552-02 ICS553 ICS554-01 ICS554-01A 13Q3 Text: DATASHEET ICS554-01A LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT Description Features The ICS554-01A is a low skew clock buffer with a single complimentary PECL input to four PECL outputs. Part of IDT’s Clock BlocksTM family, this is our lowest skew PECL	Original	ICS554-01A ICS554-01A ICS554-01, ICS553 ICS552-02 MK74CBxxx ics554 clock buffer ICS554-01 13Q3	PDF
MK74CBxxx Abstract: ICS552-02 ICS553 ICS554-01 ICS554-01A Text: DATASHEET ICS554-01A LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT Description Features The ICS554-01A is a low skew clock buffer with a single complimentary PECL input to four PECL outputs. Part of ICS’ Clock BlocksTM family, this is our lowest skew PECL	Original	ICS554-01A ICS554-01A ICS554-01, ICS553 ICS552-02 MK74CBxxx 199707558G ICS554-01	PDF
Untitled Abstract: No abstract text available Text: ICS554-01A LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT Description Features The ICS554-01A is a low skew clock buffer with a single complimentary PECL input to four PECL outputs. Part of ICS’ Clock BlocksTM family, this is our lowest skew PECL clock buffer. The ICS554-01A is	Original	ICS554-01A ICS554-01A ICS554-01, ICS553 ICS552-02 MK74CBxxx 54-01A	PDF
554-01a Abstract: ICS552-02 ICS553 ICS554-01 ICS554-01A ICS554GI-01A ICS554GI-01AT 101904 Text: ICS554-01A LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT Description Features The ICS554-01A is a low skew clock buffer with a single complimentary PECL input to four PECL outputs. Part of ICS’ Clock BlocksTM family, this is our lowest skew PECL clock buffer. The ICS554-01A is	Original	ICS554-01A ICS554-01A ICS554-01, ICS553 ICS552-02 MK74CBxxx 54-01A 554-01a ICS554-01 ICS554GI-01A ICS554GI-01AT 101904	PDF
Untitled Abstract: No abstract text available Text: ICS554-01 EOL - DEVICE NOT RECOMMENDED FOR NEW DESIGNS LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT Description Features The ICS554-01 is a low skew clock buffer with a single complimentary PECL input to four PECL outputs. Part of ICS’ Clock BlocksTM family, this is our lowest skew	Original	ICS554-01 ICS554-01 ICS553 ICS552-02 MK74CBxxx 200MHz	PDF
ICS552-02 Abstract: ICS553 ICS554-01 ICS554G-01 ICS554G-01T MAN09 Text: ICS554-01 P R E L I M I N A RY I N F O R M AT I O N LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT Description Features The ICS554-01 is a low skew clock buffer with a single complimentary PECL input to four PECL outputs. Part of ICS’ Clock BlocksTM family, this is our lowest skew	Original	ICS554-01 ICS554-01 ICS553 ICS552-02 MK74CBxxx ICS554G-01 ICS554G-01T MAN09	PDF
S2046B Abstract: S2050 S2050A-3 Text: DEVICE SPECIFICATION S2046/S2050 S2046/S2050 GIGABIT ETHERNET CHIPSET GIGABIT PECL ETHERNET CHIPSET BiCMOS CLOCK GENERATOR GENERAL DESCRIPTION FEATURES • Functionally compliant with the 802.3z specification • S2046 transmitter incorporates phase-locked	Original	S2046/S2050 S2046 S2050 20-bit S2046B S2050A-3	PDF
S2048 Abstract: S2042 S2050 Text: DEVICE SPECIFICATION S2042/S2048 S2042/S2048 HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS BiCMOS PECL CLOCK SERIAL GENERATOR HIGH PERFORMANCE INTERFACE CIRCUITS GENERAL DESCRIPTION FEATURES • Functionally compliant with ANSI X3T11 Fibre Channel physical and transmission protocol	Original	S2042/S2048 X3T11 S2042 S2048 20-bit S2050	PDF

NEC TOSA 10G Abstract: laser stm-64 10gbps 2dbm TOSA 10G 10Gbps TOSAs 400C 850C ADN2525 STM-64 "Voltage to Current Converter" 850c be 331 Text: 10Gbps Active Back-match, Differential Laser Diode Driver ADN2525 Preliminary Technical Data FEATURES GENERAL DESCRIPTION Up to 10.7Gbps operation Very low power: Icc=157mA Typical 24 ps rise/fall times PECL/CML compatible data inputs Bias current range: 10mA to 100mA	Original	10Gbps ADN2525 157mA 100mA ADN2525 PR05077-0-9/04 MO-220-VEED-2 16-Lead CP-16-3) ADN2525ACPZ-WP NEC TOSA 10G laser stm-64 10gbps 2dbm TOSA 10G 10Gbps TOSAs 400C 850C STM-64 "Voltage to Current Converter" 850c be 331	PDF
S2044 Abstract: D10-19 S2045 Text: PRELIMINARY DEVICE SPECIFICATION S2044/S2045 S2044/S2045 GLM COMPLIANT SERIAL INTERFACE CIRCUITS GLM COMPLIANT SERIAL INTERFACE CIRCUITS BiCMOS PECL CLOCK GENERATOR FEATURES GENERAL DESCRIPTION • Complies with the electrical and link levels of the Gigabaud Link Module GLM specification	Original	S2044/S2045 X3T11 S2044 S2045 20-bit D10-19	PDF
HD-SDI deserializer 16 bit parallel Abstract: HD-SDI serializer 16 bit parallel S8401 HD-SDI deserializer 8 bit parallel S8401QF DIVIDE-BY-20 S8501 D4 Package parallel to HD-SDI 35-/parallel to HD-SDI Text: DEVICE SPECIFICATION HIGH DEFINITION SERIAL DIGITAL INTERFACE HD-SDI CHIPSET HIGH DEFINITION SERIAL DIGITAL INTERFACE (HD-SDI) CHIPSET BiCMOS PECL CLOCK GENERATOR FEATURES • • • • • • • • • • • • S8401/S8501 S8401/S8501 GENERAL DESCRIPTION	Original	S8401/S8501 20-bit HD-SDI deserializer 16 bit parallel HD-SDI serializer 16 bit parallel S8401 HD-SDI deserializer 8 bit parallel S8401QF DIVIDE-BY-20 S8501 D4 Package parallel to HD-SDI 35-/parallel to HD-SDI	PDF
5-2736 Abstract: LU3X51FT transistor 5-2736 MR30 MR31 REF10 LC10 LC100 LU3M38 manchester Text: Data Sheet July 2000 FASTCAT TM LU3X51FT Ethernet Transceiver 10/100Base-TX/FX Features 100 Mbits/s FX Transceiver 10 Mbits/s Transceiver • Compatible with IEEE 802.3u 100Base-FX standard ■ Reuses existing twisted-pair I/O pins for compatible fiber-optic transceiver pseudo-ECL PECL	Original	LU3X51FT 10/100Base-TX/FX 100Base-FX 10Base-T 10Base-T DS00-353LAN DS99-032LAN) 5-2736 LU3X51FT transistor 5-2736 MR30 MR31 REF10 LC10 LC100 LU3M38 manchester	PDF
ST 358 Abstract: "network interface cards" Text: Advance Data Sheet October 1998 FASTCAT TM LU3X51FT Ethernet Transceiver 10/100Base-TX/FX Features 100 Mbits/s FX Transceiver 10 Mbits/s Transceiver • Compatible with IEEE 802.3u 100Base-FX standard ■ Reuses existing twisted-pair I/O pins for compatible fiber-optic transceiver pseudo-ECL PECL	Original	LU3X51FT 10/100Base-TX/FX 100Base-FX 10Base-T DS99-032LAN DS98-064LAN) ST 358 "network interface cards"	PDF
Untitled Abstract: No abstract text available Text: 5420 series VCXO Module ICs with Built-in Varicap OVERVIEW The 5420 series are LV-PECL output VCXO ICs that provide a wide frequency pulling range. They employ bipolar oscillator circuit and recently developed varicap diode fabrication process that provides a low phase noise characteristic and a wide frequency pulling range	Original	250MHz ND14003-E-00	PDF
Untitled Abstract: No abstract text available Text: * S O NET OC-12/OC-3 CLO C K SYNTHESIZER SYNERGY SEMICONDUCTOR Clockworks SY89426 DESCRIPTION FEATURES • Single chip source for 622.08MHz and 155.52MHz clocks ■ 622.08MHz output is differential PECL, 155.52MHz output is single-ended PECL ■ TTL/CMOS compatible inputs and reference output	OCR Scan	OC-12/OC-3 SY89426 08MHz 52MHz 395mW 28-pin SY89426 08MHz,	PDF
Untitled Abstract: No abstract text available Text: VM 5210M • High Performance - Rise/Fall Times = 6.5 ns Typical into 1 nH Head - Input Capacitance = 10 pF Typical - Input Noise = 0.52 nV/VHz Typical - Head Inductance Range = 0 .2 -1 .5 nH - Voltage Gain = 150 V/V - Olher Options Available • PECL Write Data Lines	OCR Scan	5210M 10-CHANNEL, V/12V VM5210M	PDF
Untitled Abstract: No abstract text available Text: VM 522015C August, 1995 CON NECTION DIAGRAM • High Performance - Rise/Fall Times = 4 ns Typical into 600 nH Head - Input Capacitance = 10 pF Typical - Input Noise = 0.65 nV/VHz Typical - Head Inductance Range = 400 - 800 nH - Voltage Gain = 150 V/V • PECL Write Data Lines	OCR Scan	522015C 20-CHANNEL, V/12V VM522015C 20-channels. 100mV, 10MHz 600nH 5W12V	PDF
Untitled Abstract: No abstract text available Text: * PR O G R A M M A B LE FR EQ U EN C Y SYNTHESIZER SYNERGY Clockworks SY89429V 25MHz to 400MHz SEMICONDUCTOR DESCRIPTION FEATURES • 3.3V and 5V power supply options ■ 25MHz to 400MHz differential PECL outputs ■ ±25ps peak-to-peak output jitter	OCR Scan	25MHz 400MHz) SY89429V 400MHz AN-07) 28-pin SY89429V	PDF

PECL 554 Search Results

PECL 554 Result Highlights (5)

PECL 554 Datasheets Context Search

ICS553

ICS554-01

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ICS552-02

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ics554 clock buffer

MK74CBxxx

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554-01a

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ICS552-02

S2046B

S2048

NEC TOSA 10G

S2044

HD-SDI deserializer 16 bit parallel

5-2736

ST 358

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