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    PCI CORE Search Results

    PCI CORE Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TMPM3HMFYAFG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M3 Core Based Microcontroller/32bit/P-LQFP80-1212-0.50-003 Visit Toshiba Electronic Devices & Storage Corporation
    TMPM3HPFYADFG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M3 Core Based Microcontroller/32bit/P-LQFP128-1420-0.50-001 Visit Toshiba Electronic Devices & Storage Corporation
    TMPM3HLFYAUG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M3 Core Based Microcontroller/32bit/P-LQFP64-1010-0.50-003 Visit Toshiba Electronic Devices & Storage Corporation
    TMPM3HNFZAFG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M3 Core Based Microcontroller/32bit/P-LQFP100-1414-0.50-002 Visit Toshiba Electronic Devices & Storage Corporation
    TMPM3HLFZAUG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M3 Core Based Microcontroller/32bit/P-LQFP64-1010-0.50-003 Visit Toshiba Electronic Devices & Storage Corporation
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    PCI CORE Datasheets (1)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    PCI Core Lattice Semiconductor PCI Core Data Sheet Original PDF

    PCI CORE Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    PCI AHB DMA

    Abstract: ahb slave RTL AMBA AHB bus AMBA AHB DMA DMA with AHB PCI AHB bridge
    Text:  PCI specification 2.3 compliant  66MHz PCI performance  64-bit PCI data path PCI-M64AHB  Zero wait states burst mode  Full PCI bus master/target func- 64-bit/66MHz PCI PCI to AMBA AHB Interface Core tionality  Single PCI interrupt support


    Original     		PDF 66MHz 64-bit PCI-M64AHB 64-bit/66MHz PCI-M64AHB PCI AHB DMA ahb slave RTL AMBA AHB bus AMBA AHB DMA DMA with AHB PCI AHB bridge

    Spartan-3E XC3S1600E-4

    Abstract: vhdl code for 32bit data memory XC2V1000-4
    Text: PCI specification 2.3 compliant 33/66 MHz performance 32-bit datapath PCI-HB 32-bit/33, 66MHz PCI Host Bridge Core The PCI Host Bridge core enables data transfers between a host processor system and PCI bus based devices. The bridge is in charge of PCI bus arbitration, generating PCI


    Original     		PDF 32-bit 32-bit/33, 66MHz Spartan-3E XC3S1600E-4 vhdl code for 32bit data memory XC2V1000-4

    PCI2030

    Abstract: AD27 AD29 AD30 XCPS012 S-PQFP-G176
    Text: PCI2030 PCI-TO-PCI BRIDGE XCPS012 – DECEMBER 1997 D D D D D D D D D D D D Supports PCI Local Bus Specification 2.1 and PCI-to-PCI Bridge Specification 1.0 3.3-V Core Logic With Universal PCI Interfaces Compatible With 3.3-V and 5-V PCI Signaling Environments


    Original     		PDF PCI2030 XCPS012 32-Bit, 33-MHz PCI2030 AD27 AD29 AD30 XCPS012 S-PQFP-G176

    AD27

    Abstract: AD29 AD30 PCI2030 XCPS012
    Text: PCI2030 PCI-TO-PCI BRIDGE XCPS012 – DECEMBER 1997 D D D D D D D D D D D D Supports PCI Local Bus Specification 2.1 and PCI-to-PCI Bridge Specification 1.0 3.3-V Core Logic With Universal PCI Interfaces Compatible With 3.3-V and 5-V PCI Signaling Environments


    Original     		PDF PCI2030 XCPS012 32-Bit, 33-MHz AD27 AD29 AD30 PCI2030 XCPS012

    AD27

    Abstract: AD29 AD30 PCI2031
    Text: PCI2031 PCI-TO-PCI BRIDGE SCPS017A – DECEMBER 1997 – REVISED JANUARY 1998 D D D D D D D D D D D D D PCI Power Management Compliant ACPI 1.0 Compliant Supports PCI Local Bus Specification 2.1 and PCI-to-PCI Bridge Specification 1.0 3.3-V Core Logic With Universal PCI


    Original     		PDF PCI2031 SCPS017A 32-Bit, 33-MHz AD27 AD29 AD30 PCI2031

    south bridge

    Abstract: AD27 AD29 AD30 PCI2031 678h-67Bh S-PQFP-G176
    Text: PCI2031 PCI-TO-PCI BRIDGE SCPS017A – DECEMBER 1997 – REVISED JANUARY 1998 D D D D D D D D D D D D D PCI Power Management Compliant ACPI 1.0 Compliant Supports PCI Local Bus Specification 2.1 and PCI-to-PCI Bridge Specification 1.0 3.3-V Core Logic With Universal PCI


    Original     		PDF PCI2031 SCPS017A 32-Bit, 33-MHz south bridge AD27 AD29 AD30 PCI2031 678h-67Bh S-PQFP-G176

    AD27

    Abstract: AD29 AD30 PCI2031 XCPS017
    Text: PCI2031 PCI-TO-PCI BRIDGE XCPS017 – DECEMBER 1997 D D D D D D D D D D PCI Power Management Compliant ACPI 1.0 Compliant Supports PCI Local Bus Specification 2.1 and PCI-to-PCI Bridge Specification 1.0 3.3-V Core Logic With Universal PCI Interfaces Compatible With 3.3-V and 5-V


    Original     		PDF PCI2031 XCPS017 32-Bit, 33-MHz AD27 AD29 AD30 PCI2031 XCPS017

    PCI Express

    Abstract: northwest logic pci express verification for pci express PCI express design pci root complex DMA engine PCI express x1 specification
    Text: PCI Express Complete Core Block Diagram • Combines Northwest Logic’s PCI Express Core and PCI Express Back-End for a complete, easy-to-use PCI Express Solution PCI Express Back-End • x1, x4, x8 lane versions available • Comprehensive PCI Express PHY support


    Original     		PDF

    XC6SLX9

    Abstract: Spartan6 XC6SLX9 XC6SL* MEMORY spartan 3e xc3s500e XC3S500E
    Text: Fully compliant with the PCI Local Bus Specification, Revision 2.3. PCI-M32MF Multi-Function PCI Master/Target Interface Core The PCI-M32MF implements a master/target PCI interface compliant with the PCI 2.3 specification. It supports a 32-bit address/data bus and operates up to 33 MHz 66 MHz


    Original     		PDF PCI-M32MF PCI-M32MF 32-bit XC6SLX9 Spartan6 XC6SLX9 XC6SL* MEMORY spartan 3e xc3s500e XC3S500E

    CAN protocol basics

    Abstract: design desktop motherboard tutorial XC2S50 driver pci card schematic diodes PCI I/O interface PAR64 PCI64 64-BIT SOUND CARD REQ64
    Text: PCI Tutorial PCI Basics - Slide 1 2000 Xilinx, Inc. All Rights Reserved Agenda PCI Fundamentals PCI Local Bus Architecture PCI Configuration PCI Signals Electrical and Timing Specifications Basic Bus Operations 64-bit Extension PCI Addressing and Bus Commands


    Original     		PDF 64-bit 66-MHz differen2000 CAN protocol basics design desktop motherboard tutorial XC2S50 driver pci card schematic diodes PCI I/O interface PAR64 PCI64 64-BIT SOUND CARD REQ64

    pci core

    Abstract: Soft Core RTL FIFO synchronous fifo design in verilog
    Text: PCI Peripheral Core PCI ADOUT Register Core Block Diagram PCI Parity Multiplexer Register Master Write FIFO PCI Bus Register Master Read FIFO Master State Machine/ DMA Register Master Request FIFO Output Mux Application Interface PCI I/O Cells ▼ Configuration


    Original     		PDF 32-bit 64-bit ASIC-FS-20827-10/99 pci core Soft Core RTL FIFO synchronous fifo design in verilog

    AMBA BUS vhdl code

    Abstract: amba ahb bus arbitration AMBA AHB memory controller AMBA AHB bus arbiter PCI AHB bridge ahb slave RTL vhdl code AMBA AHB interrupt controller in vhdl code AMBA AHB bus bus arbiter
    Text: PCI specification 2.3 compliant 33/66 MHz performance 32-bit datapath PCI-HB-AHB PCI reset generator PCI bus arbiter up to 7 external bus agents 32-bit, 33/66MHz PCI AMBA AHB Host Bridge Core Interrupt controller Parity generation and parity error detection.


    Original     		PDF 32-bit 32-bit, 33/66MHz AMBA BUS vhdl code amba ahb bus arbitration AMBA AHB memory controller AMBA AHB bus arbiter PCI AHB bridge ahb slave RTL vhdl code AMBA AHB interrupt controller in vhdl code AMBA AHB bus bus arbiter

    D00H

    Abstract: REQ64
    Text: PCI-to-PCI Bridge 14 This chapter describes the PCI-to-PCI Bridge including functionality, modes of operation, configuration, and integration into the i960 RM/RN I/O processor system architecture. 14.1 Overview The PCI-to-PCI bridge unit extends a PCI Bus beyond its physical constraint of ten electrical PCI


    Original     		PDF

    nvidia G86

    Abstract: DMS59 DMS-59 1920x1200 nvidia g86-730 DMS59 to vga 2048X1536 P383 NV44NVS VCQ440NVS-PCX16BLK-1
    Text: NVIDIA QUADRO NVS by PNY TECHNOLOGIES Dual - Monitor www.pny.eu Bus Connector NVS 280 PCI P169 NVS 285 PCI-E x1 (P583) Quad - Monitor NVS 285 PCI-E x16 (P383) NVS 290 PCI-E x1 (P558) NVS 290 PCI-E x16 (P538) NVS 440 PCI-E (P498) NVS 440 PCI-E (P307) PCI


    Original     		PDF G86-825 DMS59 2048x1536 1920x1200 VCQ290NVS-PCX1-PB VCQ290NVS-PCX1BLK-1 nvidia G86 DMS-59 1920x1200 nvidia g86-730 DMS59 to vga 2048X1536 P383 NV44NVS VCQ440NVS-PCX16BLK-1

    SPARTAN-3 XC3S400

    Abstract: vhdl code dma controller XC3S400 vhdl code for parity checker PCI-M32 Spartan 3E VHDL code VIRTEX-5 xc5vlx50 vhdl code for 6 bit parity generator vhdl code for bram XC3S250E
    Text: Flexible synthesizable VHDL PCI specification 2.3 compliant PCI-M32 32-bit/33MHz PCI Master/Target Interface Core The main PCI-M32 Interface core purpose is to isolate the user from having to solve complex problems of the PCI interface implementation and let the user instead focus on


    Original     		PDF PCI-M32 32-bit/33MHz PCI-M32 32-bit SPARTAN-3 XC3S400 vhdl code dma controller XC3S400 vhdl code for parity checker Spartan 3E VHDL code VIRTEX-5 xc5vlx50 vhdl code for 6 bit parity generator vhdl code for bram XC3S250E

    vhdl code dma controller

    Abstract: VHDL code for pci vhdl code for DMA application of parity checker design of dma controller using vhdl PCI-M32
    Text: Flexible synthesizable VHDL PCI specification 2.3 compliant PCI-M32 32-bit/33MHz PCI Master/Target Interface Core The main PCI-M32 Interface core purpose is to isolate the user from having to solve complex problems of the PCI interface implementation and let the user instead focus on


    Original     		PDF PCI-M32 32-bit/33MHz PCI-M32 32-bit vhdl code dma controller VHDL code for pci vhdl code for DMA application of parity checker design of dma controller using vhdl

    slot machine block diagram vhdl

    Abstract: MPCI32 vhdl code dma controller ,vhdl code for implementation of eeprom 32Bit verilog code for pci to pci bridge pci verilog code verilog code for EEPROM Controller
    Text: Inventra MPCI32 Soft Core RTL IP 32bit 33/66MHz PCI Core w/Cardbus support PCI Bus / Cardbus D A T A S H E E T Major Product Features: • Fully compliant with PCI v2.2 specification PCI Core for Peripheral Apps. PCI Bus Interface Target Register Interface


    Original     		PDF MPCI32 32bit 33/66MHz PD-40100 003-FO slot machine block diagram vhdl MPCI32 vhdl code dma controller ,vhdl code for implementation of eeprom verilog code for pci to pci bridge pci verilog code verilog code for EEPROM Controller

    SLC88B17

    Abstract: No abstract text available
    Text: SLC88B17 ADVANCE INFORMATION PCI-ISA Bridge Chip FEATURES 5 Volt Operation PCI 2.1 Compliant PCI to ISA bridge - Supports 33MHz PCI bus Supports Full ISA at ¼ of PCI Frequency Supports Full Subtractive Decode of PCI Supports up to 5 ISA Slots Supports PC/PCI DMA Protocol


    Original     		PDF SLC88B17 33MHz SLC88B17QFP SLC88B17

    LAB2

    Abstract: No abstract text available
    Text: PCI Core Basics pci18000-4-ILT v1.0 September 08, 2003 Course Specification Course Description This PCI training course gives you an introduction to basic PCI concepts and architecture. This course emphasizes and illustrates how PCI transactions take place. It also gives you an overview of Xilinx PCI


    Original     		PDF pci18000-4-ILT 64-Bit 66-MHz LAB2

    Untitled

    Abstract: No abstract text available
    Text:  PCI specification 2.3 compliant  33/66 MHz performance  32-bit datapath PCI-HB 32-bit/33, 66Mhz PCI Host Bridge Core  PCI reset generator  PCI bus arbiter up to 7 external bus agents  Interrupt controller  Parity generation and parity


    Original     		PDF 32-bit 32-bit/33, 66Mhz

    application of parity checker

    Abstract: design of dma controller using vhdl PCI-M32 vhdl code it parity generator sample vhdl code for memory write VHDL code for pci RTAX250S
    Text: Flexible synthesizable VHDL PCI specification 2.3 compliant PCI-M32 32-bit/33MHz PCI Master/Target Interface Core The main PCI-M32 Interface core purpose is to isolate the user from having to solve complex problems of the PCI interface implementation and let the user instead focus on


    Original     		PDF PCI-M32 32-bit/33MHz PCI-M32 32-bit application of parity checker design of dma controller using vhdl vhdl code it parity generator sample vhdl code for memory write VHDL code for pci RTAX250S

    AD10

    Abstract: AD11 AD12 PCI2050 PCI2050A
    Text: PCI2050A PCI-to-PCI BRIDGE SCPS067 – MAY 2001 D D D D D D D Two 32-Bit, 66-MHz PCI Buses Configurable for PCI Power Management Interface Specification Provides CompactPCI Hot-Swap Functionality 3.3-V Core Logic With Universal PCI Interfaces Compatible With 3.3-V and 5-V


    Original     		PDF PCI2050A SCPS067 32-Bit, 66-MHz AD10 AD11 AD12 PCI2050 PCI2050A

    ACP11

    Abstract: No abstract text available
    Text: PCI2031 PCI-TO-PCI BRIDGE SCPSQ17A - DECEMBER 1997 - REVISED JANUARY 1998 PCI Power Management Compliant ACP11.0 Compliant Supports PCI Local Bus Specification 2.1 and PCI-to-PCI Bridge Specification 1.0 3.3-V Core Logic With Universal PCI Interfaces Compatible With 3.3-V and 5-V


    OCR Scan     		PDF PCI2031 SCPSQ17A ACP11 32-Bit, 33-MHz

    be3sc

    Abstract: No abstract text available
    Text: PCI2030 PCI-TO-PCI BRIDGE XCPS012 -D E C E M B E R 1997 • Supports PCI Local Bus Specification 2.1 and PCI-to-PCI Bridge Specification 1.0 • • • • • • • • • 3.3-V Core Logic With Universal PCI Interfaces Compatible With 3.3-V and 5-V


    OCR Scan     		PDF PCI2030 XCPS012 32-Bit, 33-MHz be3sc