PASSIVE DELAY LINE 16 PIN 10 TAPS Search Results

PASSIVE DELAY LINE 16 PIN 10 TAPS Result Highlights (5)

Part	Manufacturer	Description
NFMJMPC226R0G3D	Murata Manufacturing Co Ltd	Data Line Filter,
NFM15PC755R0G3D	Murata Manufacturing Co Ltd	Feed Through Capacitor,
NFM15PC435R0G3D	Murata Manufacturing Co Ltd	Feed Through Capacitor,
NFM15PC915R0G3D	Murata Manufacturing Co Ltd	Feed Through Capacitor,
GCM033C70J104KE02J	Murata Manufacturing Co Ltd	0201 (0603M) X7S (EIA) 6.3Vdc 0.1μF±10%

PASSIVE DELAY LINE 16 PIN 10 TAPS Datasheets Context Search

Catalog Datasheet	MFG & Type	PDF	Document Tags
Delay Lines Abstract: SMD 0505 RESISTOR 10K OHMS SMD transistor M05 equivalent ZO 607 TZB12-5 TF80 AMY-5 analog delay line schematic AML1-12-10 PLDM7-2.5 Text: Rhombus Industries Inc. 2002 Transformers & Magnetic Products Delay Lines Electromagnetic ∆t Logic Buffered Delay Low Distortion Buffered Input / Output Fast Rise Times 5V FAST/TTL & Advanced CMOS Single Output 5 Taps 10 Taps 16 Taps 20 Taps 3V Logic, Low Voltage CMOS	Original	PDF	DLCAT-2002-01 Delay Lines SMD 0505 RESISTOR 10K OHMS SMD transistor M05 equivalent ZO 607 TZB12-5 TF80 AMY-5 analog delay line schematic AML1-12-10 PLDM7-2.5
Active (Logic Buffered) Abstract: AML12-1 SP24L10005 SMD transistor M05 AMY-5 LVMDM-45G PLDM7-2.5 SMD 0505 RESISTOR 10K OHMS smd 2d 1002 -reel TZB4* "cross reference" Text: Rhombus Industries Inc. 2001 Transformers & Magnetic Products Delay Lines Electromagnetic ∆t Logic Buffered Delay Low Distortion Buffered Input / Output Fast Rise Times 5V FAST/TTL & Advanced CMOS Single Output 5 Taps 10 Taps 16 Taps 20 Taps 3V Logic, Low Voltage CMOS	Original	PDF	DLCAT-2001-01 Active (Logic Buffered) AML12-1 SP24L10005 SMD transistor M05 AMY-5 LVMDM-45G PLDM7-2.5 SMD 0505 RESISTOR 10K OHMS smd 2d 1002 -reel TZB4* "cross reference"
DLM5 Abstract: dlm_tf 2SA1927 TF100-10 TF400-10 TF80 125OC TF100-5 TF120-5 TF150-5 Text: Fast Rise Time td / tr TF Series Fast tr High Performance 20 Section 10-Tap 28-Pin Delay Lines High Bandwidth 10 0.35 / tr Low Distortion LC Network 10 Equal Delay Taps Standard Impedances: 50 - 75 - 100 - 200 Ω Stable Delay vs. Temperature: 100 ppm/OC	Original	PDF	10-Tap 28-Pin -55OC 125OC D14-300 DLM5 dlm_tf 2SA1927 TF100-10 TF400-10 TF80 125OC TF100-5 TF120-5 TF150-5
2214-120C Abstract: 2214-200C 2214-300C 2214-400C 2214-40C 2214-500C 2214-600C 2214-80C Text: 2214 20-TAP DIP DELAY LINE TD/TR = 10 SERIES 2214 data 3  delay devices, inc. FEATURES • • • • • PACKAGES 20 taps of equal delay increment High bandwidth (TD/TR =10) Low profile Epoxy encapsulated Meets or exceeds MIL-D-23859C N/C 1 24 N/C IN	Original	PDF	20-TAP MIL-D-23859C 2214-xxz 2214-xxzC4 T1-T20 2214-series devi00ns 1000ns 2214-120C 2214-200C 2214-300C 2214-400C 2214-40C 2214-500C 2214-600C 2214-80C
Untitled Abstract: No abstract text available Text: 2214 data 3  delay devices, inc. 20-TAP DIP DELAY LINE TD/TR = 10 SERIES 2214 FEATURES • • • • • PACKAGES 20 taps of equal delay increment High bandwidth (TD/TR =10) Low profile Epoxy encapsulated Meets or exceeds MIL-D-23859C N/C 1 24 N/C IN	Original	PDF	20-TAP MIL-D-23859C 2214-xxz 2214-xxzC4 T1-T20 2214-series 1000ns
400d Abstract: No abstract text available Text: 2214 data 3  delay devices, inc. 20-TAP DIP DELAY LINE TD/TR = 10 SERIES 2214 FEATURES • • • • • PACKAGES 20 taps of equal delay increment High bandwidth (TD/TR =10) Low profile Epoxy encapsulated Meets or exceeds MIL-D-23859C N/C 1 24 N/C IN	Original	PDF	20-TAP MIL-D-23859C 2214-xxz 2214-xxzC4 T1-T20 2214-series 1000ns 400d
400d Abstract: 2214-120C 2214-200C 2214-300C 2214-400C 2214-40C 2214-500C 2214-600C 2214-80C Text: 2214 data 3  delay devices, inc. 20-TAP DIP DELAY LINE TD/TR = 10 SERIES 2214 FEATURES • • • • • PACKAGES 20 taps of equal delay increment High bandwidth (TD/TR =10) Low profile Epoxy encapsulated Meets or exceeds MIL-D-23859C N/C 1 24 N/C IN	Original	PDF	20-TAP MIL-D-23859C 2214-xxz 2214-xxzC4 T1-T20 2214-series 100ns 1000ns 400d 2214-120C 2214-200C 2214-300C 2214-400C 2214-40C 2214-500C 2214-600C 2214-80C
1519-20A Abstract: 1519-25A 1519-30A 1519-40A 1519-45A 1519-50A 1519-60A 1519-75A Text: 1519 data 3  delay devices, inc. 10-TAP DIP DELAY LINE TD/TR = 5 SERIES 1519 FEATURES • • • • • • PACKAGES 10 taps of equal delay increment Delays as large as 300ns available Low DC resistance Standard 14-pin DIP package Epoxy encapsulated	Original	PDF	10-TAP 300ns 14-pin MIL-D-23859C 1519-series T1-T10) dev00ns 1519-20A 1519-25A 1519-30A 1519-40A 1519-45A 1519-50A 1519-60A 1519-75A
1519 Abstract: No abstract text available Text: 1519 10-TAP DIP DELAY LINE TD/TR = 5 SERIES 1519 FEATURES •      PACKAGES 10 taps of equal delay increment Delays as large as 300ns available Low DC resistance Standard 16-pin DIP package Epoxy encapsulated Meets or exceeds MIL-D-23859C	Original	PDF	10-TAP 300ns 16-pin MIL-D-23859C 1519-xxz 1519-series T1-T10) 1000ns 1519
80P-20051XX Abstract: 80P-02012XX 80P-02051XX 80P-04012XX 80P-04051XX 80P-06051XX 80P-08012XX 80P-08051XX 80P-10051XX Text: Allenavionics 80P Series 24 Pin Dual-In-Lline Series 80P - Passive 24 Pin DIP Delay Line page a-ddl-80p Allenavionics 24 Pin DIP Package Risetime: 10% maximum of total delay see Table1 Characteristic Impedance: 50, 100 & 200 Ohms ±10% 20 Equally Spaced Taps	Original	PDF	a-ddl-80p 2000ns 100ppm/ 50VDC 80P-120012XX 80P-150012XX 80P-04022XX 80P-06022XX 80P-08022XX 80P-10022XX 80P-20051XX 80P-02012XX 80P-02051XX 80P-04012XX 80P-04051XX 80P-06051XX 80P-08012XX 80P-08051XX 80P-10051XX
20p03 Abstract: 20P06 passive delay line Text: Yuan Dean Scientific CO.,LTD 7 PIN SINGLE-IN-LINE PASSIVE DELAY LINE FEATURES 20P SERIES •7-PIN SIP PACKAGE. •5EQUALLY-SPACED TAPS. •OPERATING TEMPERATURE RANGE:0℃ TO +70℃ •LOW OUTPUT DISTORTION:±10%. •TOTAL DELAYS FROM5-100Ns	Original	PDF	FROM5-100Ns 100nS 100ppm/ 20P-005XX 20-030XX 20P-040XX 20P-050XX 20P-060XX 20P-070XX 20P-080XX 20p03 20P06 passive delay line
Untitled Abstract: No abstract text available Text: • • • • • • • T2L LV CMOS input and outputs Delays stable and precise 8-pin Space Saver package Leads - thru-hole, J, Gull Wing or Tucked Available in delays from 8 to 150ns Output and 2 intermediate taps each isolated and with 12mA output drive capability	Original	PDF	150ns C/022197R
LPF12A0 Abstract: 5b1c ksd 7400 F585 -32 8116 RAM 1d77 6F12 5a0b x768 BB52 Text: CXD2728Q Single-Chip Dolby Pro Logic Surround Decoder Preliminary Description The CXD2728Q is a CMOS LSI developed for Dolby Pro Logic Surround. A SRAM for short delay and AD/DA converters are built in, and all functions necessary for Dolby Pro Logic Surround such as an	Original	PDF	CXD2728Q CXD2728Q 32K-bit SQA12 80PIN 42/COPPER QFP-80P-L01 QFP080-P-1420 LPF12A0 5b1c ksd 7400 F585 -32 8116 RAM 1d77 6F12 5a0b x768 BB52
analog delay line Abstract: No abstract text available Text: PASSIVE DELAY LINES, SIP PACKAGE RESISTORS CAPACITORS COILS DELAY LINES SP05 SERIES - 7 PIN, 5 TAP SP10 SERIES - 14 PIN, 10 TAP FEATURES Low cost, prompt delivery! Wide variety of values, 5nS to 250nS Precision-grade internal inductor elements ensure excellent stability	Original	PDF	250nS MIL-D23859. GF-061. analog delay line

ksd 9700 Abstract: 5a0b C400H 4155 cmos 5b1c e32f e729 CXD2728Q krd 1600 65B4 Text: CXD2728Q Single-Chip Dolby Pro Logic Surround Decoder Description The CXD2728Q is a CMOS LSI developed for Dolby Pro Logic Surround. A SRAM for short delay and AD/DA converters are built in, and all functions necessary for Dolby Pro Logic Surround such as an	Original	PDF	CXD2728Q CXD2728Q 32K-bit oth39 80PIN QFP-80P-L01 QFP080-P-1420 42/COPPER ksd 9700 5a0b C400H 4155 cmos 5b1c e32f e729 krd 1600 65B4
ksd 9700 Abstract: CXD2724Q SQC06 SQD15 5b1c ne5522 5A0B CXD2724AQ-1 SQC14 2F18 Text: CXD2724AQ-1 Single-Chip Dolby Pro Logic Surround Decoder For the availability of this product, please contact the sales office. Description The CXD2724AQ-1 is a CMOS LSI developed for Dolby Pro Logic Surround. A SRAM for short delay and AD/DA converters are built in, and all functions	Original	PDF	CXD2724AQ-1 CXD2724AQ-1 80PIN QFP-80P-L01 QFP080-P-1420 42/COPPER ksd 9700 CXD2724Q SQC06 SQD15 5b1c ne5522 5A0B SQC14 2F18
Untitled Abstract: No abstract text available Text: A LLE N A V IO N IC S, INC. SIP 10 TAPS 14 PIN PASSIVE SIP 5 TAPS 7 PIN PASSIVE SIP 1 TAPS 3 PIN PASSIVE 20P 21P 22P SPECIFICATIONS: • Operating Temperature Range: O’C to +70°C -55°C to +125°C up on request •Storage Temperature Range:-65T to +125"C.	OCR Scan	PDF	ohms/50V
TF50-10 Abstract: No abstract text available Text: Fast Rise Time t j t ~ 1 0 TF Series Fast tr High Performance 20 Section 10-Tap 28-Pin Delay Lines High Bandwidth ~ 0.35 / f Low Distortion LC Network 10 Equal Delay Taps Standard Impedances: 50 - 7 5 - 100 - 200 Q. Stable Delay vs. Temperature: 100 ppm PC	OCR Scan	PDF	10-Tap 28-Pin D14-300 TF50-10
MIL-STD-454E Abstract: Military Standard, Test Methods and Procedures fo passive delay line 16 pin 10 taps JBM Electronics L-22-132 F16H Text: Military Hi-Reliability QUALITY PROGRAM J B M ' s Q u a l i t y A s s u r a n c e P r o g r a m is d e s i g n e d t o f u l l y c o m p l y w i t h t h e f o l l o w i n g m i l i t a r y s p e c i f i c a t i o n s : 1. MIL-I-45208A 2. MIL-STD-45662 Inspection System Requirements	OCR Scan	PDF	MIL-I-45208A MIL-STD-45662 MIL-STD-454E MIL-STD-810C MIL-STD-202F MIL-STD-883C L-22-132 L-22-209 D-88-01 D-88-77 Military Standard, Test Methods and Procedures fo passive delay line 16 pin 10 taps JBM Electronics F16H
ATIC 112 Abstract: No abstract text available Text: Fast Rise Time td/ t ~ 10 TF Series Fast tr High Performance 20 Section 10-Tap 28-Pin Delay Lines High Bandwidth ~ 0.35 / f Low Distortion LC Network 10 Equal Delay Taps Standard Impedances: 50 - 7 5 - 100 - 200 Q Stable Delay vs. Temperature: 100 ppm/°C	OCR Scan	PDF	10-Tap 28-Pin D14-300 ATIC 112
Untitled Abstract: No abstract text available Text: Electromagnetic Delay Lines Ultra Low Attenuation and Distortion Total Delays up to 1000ns, Fast Rise Times Temperature Stability, 70 ppm/°C Typical. Single, 5 ,1 0 ,1 6 & 20 Tap Standard Configurations Operating Temperature Range: 55 to +125°C Standard Impedances from 50 to 200 Ohms	OCR Scan	PDF	1000ns, PASSIVE-S/93
uPD9306 Abstract: upd7261 9306A upd9306a harddisk power supply CIRCUIT diagram harddisk schematic Text: NEC mPD9306IA CMOS HARD-DISK INTERFACE NEC Electronics Inc. Description Pin Identification The nPD9306 and piPD9306A hard-disk interface HDI chips are unique CM O S single-chip support devices in tended for use with the /¿PD7261A hard-disk controller.	OCR Scan	PDF	uPD9306 uPD9306A uPD7261A nPD9306/A PD9306/A ST-506 iPD9306/A mPD9306/A HPD9306/A 30-ns upd7261 9306A harddisk power supply CIRCUIT diagram harddisk schematic
L26XX Abstract: L2671 L-26-116 L-26-115 26160 L-26-67 L26128 Text: Passive Delay Lines Delay Range 5-450 nsec STYLE L-26 14-pin SIP 10 equally-spaced taps Td/Tr = 5:1 (typ.) For test conditions see page 16. Compatible With Various Logic Systems including TTL and Video Circuits. CONNECTION Total Delay Tolerance = ± 5% or	OCR Scan	PDF	14-pin 100PPM/ MIL-D-23859 L-26-87 L-26-57 L-26-117 L-26-157 L-26-88 L-26-58 L-26-158 L26XX L2671 L-26-116 L-26-115 26160 L-26-67 L26128
200ns 10 tap Abstract: No abstract text available Text: A LLEN A V IO N IC S, INC. DIP 24 PIN 20 TAP PASSIVE DELAY LINE 24P SPECIFICATIONS: MECHANIC: Total Delay:20 to 1000 ns Tap Delays:5% increments of total delay Characteristic lmpedance:50 to 200 ohms ± 10% Distoriton: ± 10% max. Temperature Coefficient of Delay: 100 ppm/C max.	OCR Scan	PDF	50VDC, 50VDC 24-pin 24PCB50112 24PCB60112 24PCB80112 24PCB40022 24PCB60022 24PCB80022 24PCB10122 200ns 10 tap

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PASSIVE DELAY LINE 16 PIN 10 TAPS Search Results

PASSIVE DELAY LINE 16 PIN 10 TAPS Result Highlights (5)

PASSIVE DELAY LINE 16 PIN 10 TAPS Datasheets Context Search

Delay Lines

Active (Logic Buffered)

DLM5

2214-120C

Untitled

400d

400d

1519-20A

1519

80P-20051XX

20p03

Untitled

LPF12A0

analog delay line

ksd 9700

ksd 9700

Untitled

TF50-10

MIL-STD-454E

ATIC 112

Untitled

uPD9306

L26XX

200ns 10 tap