Untitled
Abstract: No abstract text available
Text: 74ACT11656 OCTAL BUFFER/LINE DRIVER WITH PARITY CHECKER/GENERATOR AND 3-STATE OUTPUTS SCAS460A – DECEMBER 1994 – REVISED APRIL 1996 D D D D D D DW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Combines ’244 and ’280 Functions In One Package
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74ACT11656
SCAS460A
500-mA
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Untitled
Abstract: No abstract text available
Text: SN54LS280, SN54S280, SN74LS280, SN74S280 9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS SDLS152 – DECEMBER 1972 – REVISED MARCH 1988 Copyright 1988, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments
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SN54LS280,
SN54S280,
SN74LS280,
SN74S280
SDLS152
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M368L1624DTL
Abstract: No abstract text available
Text: M368L1624DTL 184pin Unbuffered DDR SDRAM MODULE 128MB DDR SDRAM MODULE 16Mx64 based on 16Mx16 DDR SDRAM Unbuffered 184pin DIMM 64-bit Non-ECC/Parity Revision 0.1 May. 2002 Rev. 0.1 May. 2002 M368L1624DTL 184pin Unbuffered DDR SDRAM MODULE Revision History
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M368L1624DTL
184pin
128MB
16Mx64
16Mx16
64-bit
M368L1624DTL
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A048
Abstract: DM9348
Text: MICROCIRCUIT DATA SHEET Original Creation Date: 03/30/99 Last Update Date: 07/30/99 Last Major Revision Date: 03/30/99 MNDM9348-X REV 1A0 12-Input Parity Checker/Generator General Description The '9348 is a 12-input parity checker/generator generating odd and even parity outputs.
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MNDM9348-X
12-Input
DM9348
DM9348J/883
DM9348W/883
MIL-STD-883,
M0003348
A048
DM9348
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54F280
Abstract: 54F280DMQB 54F280FMQB 54F280LMQB F280 M280
Text: MILITARY DATA SHEET Original Creation Date: 04/19/96 Last Update Date: 07/30/96 Last Major Revision Date: 04/19/96 MN54F280-X REV 1A0 9-Bit Parity Generator /Checker General Description The F280 is a high-speed parity generator/checker that accepts nine bits of input data and
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MN54F280-X
54F280
54F280DMQB
54F280FMQB
54F280LMQB
MIL-STD-883,
-55/125C
54F280
54F280DMQB
54F280FMQB
54F280LMQB
F280
M280
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DDR200
Abstract: DDR266A DDR266B M312L2923MT0
Text: M312L2923MT0 184pin 1U Registered DDR SDRAM MODULE 1GB DDR SDRAM MODULE 128Mx72(64Mx72*2 bank based on 64Mx8 DDR SDRAM) Registered 184pin DIMM 72-bit ECC/Parity Revision 0.2 Jan. 2002 Rev. 0.2 Jan. 2002 M312L2923MT0 184pin 1U Registered DDR SDRAM MODULE
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M312L2923MT0
184pin
128Mx72
64Mx72
64Mx8
72-bit
DDR266A
DDR200
DDR266A
DDR266B
M312L2923MT0
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DDR2-667
Abstract: SSTUA32864 SSTUA32866 SSTUA32S865 TFBGA160
Text: SSTUA32S865 1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-667 RDIMM applications Rev. 02 — 16 March 2007 Product data sheet 1. General description The SSTUA32S865 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank by four 2R x 4 and similar high-density Double Data Rate 2 (DDR2) memory
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SSTUA32S865
28-bit
DDR2-667
SSTUA32S865
14-bit
DDR2-667
SSTUA32864
SSTUA32866
TFBGA160
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54ACTQ657
Abstract: No abstract text available
Text: 54ACTQ657 Quiet Series Octal Bidirectional Transceiver with 8-Bit Parity Generator/Checker and TRI-STATE Outputs General Description Features The ACTQ657 contains eight non-inverting buffers with TRI-STATE outputs and an 8-bit parity generator/checker. Intended for bus oriented applications, the device combines
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54ACTQ657
ACTQ657
54ACTQ657
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SSTUA32864
Abstract: SSTUA32866
Text: SSTUG32868 1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-1G RDIMM applications Rev. 01 — 23 April 2007 Product data sheet 1. General description The SSTUG32868 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank
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SSTUG32868
28-bit
SSTUG32868
14-bit
SSTUA32864
SSTUA32866
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DDR2-800
Abstract: SSTUA32864 SSTUA32866 E6G3
Text: SSTUM32868 1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications Rev. 02 — 2 March 2007 Product data sheet 1. General description The SSTUM32868 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank
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SSTUM32868
28-bit
DDR2-800
SSTUM32868
14-bit
SSTUA32864
SSTUA32866
E6G3
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Untitled
Abstract: No abstract text available
Text: M470L6423DN0 200pin DDR SDRAM SODIMM 512MB DDR SDRAM MODULE 64Mx64 based on sTSOP 32Mx8 DDR SDRAM 200pin SODIMM 64bit Non-ECC/Parity Revision 0.0 May 2002 Rev. 0.0 May 2002 M470L6423DN0 200pin DDR SDRAM SODIMM Revision History Revision 0.0 (May 2002) - First release.
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M470L6423DN0
200pin
512MB
64Mx64
32Mx8
64bit
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Untitled
Abstract: No abstract text available
Text: M381L6423DTL 184pin Unbuffered DDR SDRAM MODULE 512MB DDR SDRAM MODULE 64Mx72(32Mx72*2 bank based on 32Mx8 DDR SDRAM) Unbuffered 184pin DIMM 72-bit ECC/Parity Revision 0.2 May. 2002 Rev. 0.2 May. 2002 M381L6423DTL 184pin Unbuffered DDR SDRAM MODULE Revision History
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M381L6423DTL
184pin
512MB
64Mx72
32Mx72
32Mx8
72-bit
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Untitled
Abstract: No abstract text available
Text: SN74BCT29854 8-BIT TO 9-BIT PARITY BUS TRANSCEIVER S C B S 257- SEPTEMBER 1987 - REVISED NOVEMBER 1993 DW OR NT PACKAGE • BICMOS Process With TTL Inputs and Outputs T O P V IE W • State-of-the-Art BICMOS Design Significantly Reduces Standby Current
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SN74BCT29854
Am29854
300-mil
bi723
X665303
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of ic 74180
Abstract: No abstract text available
Text: TYPES SN54180, SN74180 9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS D E C E M B E R 1 9 7 2 - R E V I S E D D E C E M B E R 1 9 83 S N 5 4 1 8 0 . . J O R W P A C K A G E SN 74180 . J O R N P A C K A G E T O P V IE W F U N C T IO N T A B L E OUTPUTS IN P U T S
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SN54180,
SN74180
of ic 74180
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Untitled
Abstract: No abstract text available
Text: 54AC11853, 74AC 11853 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS TI0157— D3473, MARCH 1990 54AC11B53 . . . JT PACKAGE 74AC11853 . . . DW OR NT PACKAGE High-Speed Bus Transceivers with Parity Generator/Checker TOP VIEW Parity Error Flag Open-Drain Output • Register for Storage of the Parity Error Flag
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54AC11853,
TI0157--
D3473,
500-mA
300-mil
54AC11B53
74AC11853
54AC11853
74AC11853
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74F286
Abstract: SN74F286
Text: SN 54F286, SN 74F286 9-BIT PARITY GENERATORS/CHECKERS WITH BUS DRIVER PARITY I/O PORT D 2 9 3 2 , M ARC H 1 9 8 7 -R E V IS E D JA N U A R Y 1 9 8 9 SN 54F286 . . . J PACKAGE SN 74F286 . . . D OR N PACKAGE • Generates Either Odd or Even Parity for Nine Data Lines
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54F286,
74F286
300-mil
54F286
74F286
SN54F286
SN74F286
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74HC658
Abstract: No abstract text available
Text: SN54HC658, SN54HC659. SN74HC658, SN74HC659 OCTAL BUS TRANSCEIVERS WITH PARITY D 2 B 3 9 . M AR C H 1 9 8 4 -R E V IS E D SEPTEMBER 1 9 8 7 • Bus Transceivers with Inverting Outputs 'HC658 or True Outputs ('HC659) • Generates a Parity Bit for A Bus and B Bus
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SN54HC658,
SN54HC659.
SN74HC658,
SN74HC659
HC658)
HC659)
300-mil
HC658/-HC659
HC367
24-BIT-WIDE
74HC658
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Untitled
Abstract: No abstract text available
Text: SN74BCT29853 8-BIT TO 9-BIT PARITY BUS TRANSCEIVER SCBS002D - SEPTEMBER 1987 - REVISED APRIL 1994 DW OR NT PACKAGE TOP VIEW BiCMOS Process With TTL Inputs and Outputs State-of-the-Art BiCMOS Design Significantly Reduces Standby Current OEA[ A1[ A2[ A3 [
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SN74BCT29853
SCBS002D
Am29853
300-mil
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t1128
Abstract: No abstract text available
Text: 54A C T 11286, 74ACT11286 9-BIT PARITY G EN E R A T O R S/C H E C K ER S WITH BU S DRIVER PARITY I/O PORTS TI0124— D3166, AUG U ST 1988— REVISED MARCH 1990 54ACT11286 . . . J PACKAGE 74ACT11286 . . . D O R N PACKAGE • Inputs are TTL-Voltage Compatible
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74ACT11286
TI0124--
D3166,
500-mA
300-mil
54ACT11286
74ACT11286
t1128
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Untitled
Abstract: No abstract text available
Text: SNS4F2B0B, SN74F280B 9-BIT PARITY GENERATORSfCHECKERS D 2 9 3 2 , A P R IL 1 9 8 6 - R E V I S E D J A N U A R Y 1 9 8 9 Generates Either Odd or Even Parity for Nine Data Lines SN 54F280B I PACKAGE SN 74F280B . . . D OR N PA CK AG E T O P VIEW I Cascadable for n-Bits Parity
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SN74F280B
54F280B
74F280B
300-mil
54F280B
74F280B
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UM82450
Abstract: No abstract text available
Text: UMC UM82450 Asynchronous Communication — Element ACE Mi Feature • Adds or deletes standard asynchronous communication bits (start, stop, and parity) to or from serial data stream ■ Full double buffering eliminates need for precise synchronization ■ Independently controlled transmit, receive, I ine status,
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UM82450
UM82450
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Untitled
Abstract: No abstract text available
Text: Philips Semlconductors-Signetics FAST 74F280A, 74F280B Document No. 853-0363 ECN No. 99142 Date of issue March 191990 Parity Checker Generator Status Product Specification 9-Bit Odd/Even Parity Generator/Checker FAST Products FEA TU RES • High impedance NPN base inputs
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74F280A
74F280B
74F280A,
74F280B
500ns
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Untitled
Abstract: No abstract text available
Text: INTEGRATED T O SH IB A 9 -BIT TECHNICAL PARITY TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT CIRCUIT TC74AC280P/F/FN DATA SILICON MONOLITHIC GENERATOR/CHECKER The TC74AC280 is an advanced high speed CMOS 9 - BIT PARITY GENERATOR fabricated with silicon gate and double layer metal wiring C2MOS technology.
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TC74AC280P/F/FN
TC74AC280
14PIN
14PIN
200mil
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74AS280
Abstract: 54ALS280 500NT
Text: TE X A S IN ST R -CLOGICJ fil ~Q§Qf723 T E X A S De| 0^1753 IN S T R LOGIC 00420^ S |~ Df- Y S ~/7 81 Ç 4 2 8 9 6 SN54ALS280, SN54AS280, SN74ALS280, SN74AS280 9-BIT PARITY GENERATORS/CHECKERS D2661, DECEMBER 1982 - REVISED MAY 1986 SN 54A LS2 80, SN 5 4 A S2 8 0 . . . J PA C K A G E
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Qf723
SN54ALS280,
SN54AS280,
SN74ALS280,
SN74AS280
D2661,
300-mil
25-LIN
81-LINE
25-line
74AS280
54ALS280
500NT
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