CDCLVP2106
Abstract: QFN-40 weight
Text: CDCLVP2106 www.ti.com. SCAS887 – SEPTEMBER 2009 12 LVPECL Output, High-Performance Clock Buffer
|
Original
|
CDCLVP2106
SCAS887
CDCLVP2106
QFN-40 weight
|
PDF
|
AA30
Abstract: AA34 AB30 M21110 PRBS MSB NCN30
Text: M21110 17 x 17 3.2 Gbps Crosspoint Switch with Input Equalization Data Sheet Features - 4 Terminal Descriptions - 5 Specification Tables - 7 Functional Description - 17 Register Information - 21 Package Information - 28 World Wide Sales Companies - 37 21110-DSH-001-B, 3/27/03
|
Original
|
M21110
21110-DSH-001-B,
AA30
AA34
AB30
M21110
PRBS MSB
NCN30
|
PDF
|
Untitled
Abstract: No abstract text available
Text: CDCLVP1216 www.ti.com . SCAS877A – MAY 2009 – REVISED JULY 2009 16 LVPECL Output, High-Performance Clock Buffer
|
Original
|
CDCLVP1216
SCAS877A
CDCLVP1216
|
PDF
|
outp32
Abstract: M21130 AA30 AA34 AB30 OUTP23 NCN30
Text: M21130 68 x 68 3.2 Gbps Crosspoint Switch with Input Equalization Data Sheet Features - 4 Terminal Descriptions - 5 Specification Tables - 8 Functional Description - 17 Register Information - 20 Package Information - 25 World Wide Sales Companies - 34 21130-DSH-001-B, 3/27/03
|
Original
|
M21130
21130-DSH-001-B,
outp32
M21130
AA30
AA34
AB30
OUTP23
NCN30
|
PDF
|
Untitled
Abstract: No abstract text available
Text: CDCLVD2108 www.ti.com SCAS905C – OCTOBER 2010 – REVISED DECEMBER 2010 Dual 1:8 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD2108 FEATURES 1 • • • • • • • • • • • • Dual 1:8 Differential Buffer Low Additive Jitter <300 fs RMS in
|
Original
|
CDCLVD2108
SCAS905C
EIA/TIA-644A
48-Pin
|
PDF
|
L510B
Abstract: L61A L110 L111 l413 l812 L410A L77A L711B L713
Text: Appl i cat i o n N ot e Designing High-Speed ATM Switch Fabrics by Using Actel FPGAs The recent upsurge of interest in Asynchronous Transfer Mode ATM is based on the recognition that it represents a new level of both speed and simplification in telecommunication networks. The most significant
|
Original
|
OUTP10
OUTP11
OUTP12
PADOUTP13
PADOUTP14
PADOUTP15
L510B
L61A
L110
L111
l413
l812
L410A
L77A
L711B
L713
|
PDF
|
CDCLVP2106
Abstract: No abstract text available
Text: CDCLVP2106 www.ti.com. SCAS887 – SEPTEMBER 2009 12 LVPECL Output, High-Performance Clock Buffer
|
Original
|
CDCLVP2106
SCAS887
CDCLVP2106
|
PDF
|
Untitled
Abstract: No abstract text available
Text: CDCLVP1216 SCAS877C – MAY 2009 – REVISED AUGUST 2011 www.ti.com 16 LVPECL Output, High-Performance Clock Buffer Check for Samples: CDCLVP1216 FEATURES DESCRIPTION • • • The CDCLVP1216 is a highly versatile, low additive jitter buffer that can generate 16 copies of LVPECL
|
Original
|
CDCLVP1216
SCAS877C
10-kHz
20-MHz
QFN-48
|
PDF
|
Untitled
Abstract: No abstract text available
Text: CDCLVP1216 SCAS877C – MAY 2009 – REVISED AUGUST 2011 www.ti.com 16 LVPECL Output, High-Performance Clock Buffer Check for Samples: CDCLVP1216 FEATURES DESCRIPTION • • • The CDCLVP1216 is a highly versatile, low additive jitter buffer that can generate 16 copies of LVPECL
|
Original
|
CDCLVP1216
SCAS877C
10-kHz
20-MHz
QFN-48
|
PDF
|
Untitled
Abstract: No abstract text available
Text: CDCLVD2108 www.ti.com SCAS905C – OCTOBER 2010 – REVISED DECEMBER 2010 Dual 1:8 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD2108 FEATURES 1 • • • • • • • • • • • • Dual 1:8 Differential Buffer Low Additive Jitter <300 fs RMS in
|
Original
|
CDCLVD2108
SCAS905C
EIA/TIA-644A
48-Pin
CDCLVD2108m/clocks
|
PDF
|
Untitled
Abstract: No abstract text available
Text: CDCLVD1212 www.ti.com SCAS901B – SEPTEMBER 2010 – REVISED JANUARY 2011 2:12 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD1212 FEATURES 1 • • • • • • • • • • • • 2:12 Differential Buffer Low Additive Jitter: <300 fs RMS in
|
Original
|
CDCLVD1212
SCAS901B
EIA/TIA-644A
40-Pin
|
PDF
|
QFN-48 LAND PATTERN
Abstract: CDCLVP1216 CDCLVP1216RGZR CDCLVP1216RGZT QFN-48
Text: CDCLVP1216 www.ti.com . SCAS877A – MAY 2009 – REVISED JULY 2009 16 LVPECL Output, High-Performance Clock Buffer
|
Original
|
CDCLVP1216
SCAS877A
10-kHz
20-MHz
QFN-48 LAND PATTERN
CDCLVP1216
CDCLVP1216RGZR
CDCLVP1216RGZT
QFN-48
|
PDF
|
M37902F8CGP
Abstract: M37902F8CHP M37902FCCGP M37902FCCHP M37902FECGP M37902FECHP M37902FGCGP M37902FGCHP M37902FHCGP M37902FHCHP
Text: Y NAR I MITSUBISHI MICROCOMPUTERS P M37902F8CGP, M37902F8CHP, M37902FCCGP, M37902FCCHP M37902FECGP, M37902FECHP, M37902FGCGP, M37902FGCHP M37902FHCGP, M37902FHCHP, M37902FJCGP, M37902FJCHP . e n. atio chang cific o spe bject t l a u fin s ot a its are is n
|
Original
|
M37902F8CGP,
M37902F8CHP,
M37902FCCGP,
M37902FCCHP
M37902FECGP,
M37902FECHP,
M37902FGCGP,
M37902FGCHP
M37902FHCGP,
M37902FHCHP,
M37902F8CGP
M37902F8CHP
M37902FCCGP
M37902FCCHP
M37902FECGP
M37902FECHP
M37902FGCGP
M37902FGCHP
M37902FHCGP
M37902FHCHP
|
PDF
|
CDCLVP1216
Abstract: CDCLVP1216RGZR CDCLVP1216RGZT QFN-48
Text: CDCLVP1216 www.ti.com . SCAS877A – MAY 2009 – REVISED JULY 2009 16 LVPECL Output, High-Performance Clock Buffer
|
Original
|
CDCLVP1216
SCAS877A
10-kHz
20-MHz
CDCLVP1216
CDCLVP1216RGZR
CDCLVP1216RGZT
QFN-48
|
PDF
|
|
|
CDCLVP2108
Abstract: CDCLVP2108RGZR CDCLVP2108RGZT QFN-48 QFN-48 LAND PATTERN QFN-48 footprint
Text: CDCLVP2108 www.ti.com . SCAS878A – MAY 2009 – REVISED JULY 2009 16 LVPECL Output, High-Performance Clock Buffer
|
Original
|
CDCLVP2108
SCAS878A
10-kHz
20-MHz
CDCLVP2108
CDCLVP2108RGZR
CDCLVP2108RGZT
QFN-48
QFN-48 LAND PATTERN
QFN-48 footprint
|
PDF
|
Untitled
Abstract: No abstract text available
Text: CDCLVD2108 www.ti.com SCAS905C – OCTOBER 2010 – REVISED DECEMBER 2010 Dual 1:8 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD2108 FEATURES 1 • • • • • • • • • • • • Dual 1:8 Differential Buffer Low Additive Jitter <300 fs RMS in
|
Original
|
CDCLVD2108
SCAS905C
EIA/TIA-644A
48-Pin
|
PDF
|
QFN-48 LAND PATTERN
Abstract: No abstract text available
Text: CDCLVP2108 SCAS878B – MAY 2009 – REVISED AUGUST 2011 www.ti.com 16 LVPECL Output, High-Performance Clock Buffer Check for Samples: CDCLVP2108 FEATURES DESCRIPTION • • • The CDCLVP2108 is a highly versatile, low additive jitter buffer that can generate 16 copies of LVPECL
|
Original
|
CDCLVP2108
SCAS878B
10-kHz
20-MHz
QFN-48
QFN-48 LAND PATTERN
|
PDF
|
Untitled
Abstract: No abstract text available
Text: Sample & Buy Product Folder Support & Community Tools & Software Technical Documents CDCLVP1216 SCAS877E – MAY 2009 – REVISED SEPTEMBER 2014 CDCLVP1216 16 LVPECL Output, High-Performance Clock Buffer 1 Features 3 Description • • • The CDCLVP1216 is a highly versatile, low additive
|
Original
|
CDCLVP1216
SCAS877E
CDCLVP1216
|
PDF
|
AGGA-2
Abstract: GLONASS SV6 357 AGGA ADSP21020 epoch sv24 sv5 357 GLONASS chip T7905E
Text: Purpose and Scope The purpose of this document is to describe the detailed functionality of the secondgeneration Advanced GPS/GLONASS ASIC, the T7905E also refered to as the AGGA-2 . It describes the functionality, its modes of operation, programming aspects,
|
Original
|
T7905E
AGGA-2
GLONASS
SV6 357
AGGA
ADSP21020
epoch
sv24
sv5 357
GLONASS chip
T7905E
|
PDF
|
40spq
Abstract: No abstract text available
Text: CDCLVD2106 www.ti.com SCAS902B – SEPTEMBER 2010 – REVISED JANUARY 2011 Dual 1:6 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD2106 FEATURES 1 • • • • • • • • • • • • Dual 1:6 Differential Buffer Low Additive Jitter: <300 fs rms
|
Original
|
CDCLVD2106
SCAS902B
EIA/TIA-644A
40-pin
CDCLVD2106
40spq
|
PDF
|
Untitled
Abstract: No abstract text available
Text: CDCLVD1212 www.ti.com SCAS901 – SEPTEMBER 2010 2:12 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD1212 FEATURES 1 • • • • • • • • • • 2:12 Differential Buffer Low Additive Jitter: <300 fs RMS in 10 kHz to 20 MHz Low Output Skew of 50 ps Max
|
Original
|
CDCLVD1212
SCAS901
EIA/TIA-644A
40-Pin
CDCLVD1212
|
PDF
|
Untitled
Abstract: No abstract text available
Text: CDCLVP2106 SCAS887A – SEPTEMBER 2009 – REVISED AUGUST 2011 www.ti.com 12 LVPECL Output, High-Performance Clock Buffer Check for Samples: CDCLVP2106 FEATURES DESCRIPTION • • • The CDCLVP2106 is a highly versatile, low additive jitter buffer that can generate 12 copies of LVPECL
|
Original
|
CDCLVP2106
SCAS887A
CDCLVP2106
|
PDF
|
Untitled
Abstract: No abstract text available
Text: CDCLVP1216 SCAS877C – MAY 2009 – REVISED AUGUST 2011 www.ti.com 16 LVPECL Output, High-Performance Clock Buffer Check for Samples: CDCLVP1216 FEATURES DESCRIPTION • • • The CDCLVP1216 is a highly versatile, low additive jitter buffer that can generate 16 copies of LVPECL
|
Original
|
CDCLVP1216
SCAS877C
CDCLVP1216
|
PDF
|
L510B
Abstract: l815 l73a L61A L713 L-612 L814 l812 L313A AC105
Text: Application Note AC105 Designing High-Speed ATM Switch Fabrics by Using Actel FPGAs The recent upsurge of interest in Asynchronous Transfer Mode ATM is based on the recognition that it represents a new level of both speed and simplification in telecommunication networks. The most significant
|
Original
|
AC105
OUTP11
OUTP10
OUTP12
PADOUTP13
PADOUTP14
PADOUTP15
L510B
l815
l73a
L61A
L713
L-612
L814
l812
L313A
AC105
|
PDF
|