MEGTRON 6 Search Results

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Catalog Datasheet	MFG & Type	PDF	Document Tags
MEGTRON 6 Abstract: AN-672 Text: Transceiver Link Design Guidelines for High-Gbps Data Rate Transmission 2013.02.15 AN-672 Subscribe Feedback As transceiver data rates increase and the unit interval time UI decrease, the end-to-end link design of a transceiver channel becomes increasingly critical to the overall performance of the link. Consider an Altera	Original	PDF	AN-672 100-Gpbs CEI-25G-LR CEI-28G-VSR. CEI-28G-VSR MEGTRON 6 AN-672
molex sfp 1 gbps Abstract: SFF-8431 Text: 2013.07.10 AN-689 High Speed Channel Design Using the SFF-8431 Protocol Subscribe Feedback This document enables engineers to design high speed channels conforming to the SFF-8431 standard. It includes a case study of a board that was designed to highlight best practices for SFF-8431 compliant channel	Original	PDF	AN-689 SFF-8431 molex sfp 1 gbps
MEGTRON 6 Abstract: CEI-11G ADC digital calibration time interleaved 56Gs ADC 30Ghz Fujitsu Batboard VLSI datasheet for DAC and ADC otu 4 MEGTRON VLSI for DAC and ADC Text: Reality Check: Challenges of mixed-signal VLSI design for high-speed optical communications Mixed-signal VLSI for 100G and beyond  100G optical transport system  Why single-chip CMOS?  So what is so difficult ?  CHAIS ADC  On-chip noise coupling	Original	PDF	ECOC2009 MEGTRON 6 CEI-11G ADC digital calibration time interleaved 56Gs ADC 30Ghz Fujitsu Batboard VLSI datasheet for DAC and ADC otu 4 MEGTRON VLSI for DAC and ADC
Untitled Abstract: No abstract text available Text: Stratix V GT Device Design Guidelines 2014.01.07 AN-681 Subscribe Send Feedback Altera’s Stratix V devices provide four duplex transceiver GT channels, each capable of a serial data rate up to 28.05 Gbps. Stratix V GT devices support chip-to-chip and chip-to-module applications. The GT	Original	PDF	AN-681 1e-15
Untitled Abstract: No abstract text available Text: Stratix V GT Device Design Guidelines 2013.03.29 AN-681 Subscribe Feedback Altera’s Stratix V devices provide four duplex transceiver GT channels, each capable of a serial data rate up to 28.05 Gbps. Stratix V GT devices support chip-to-chip and chip-to-module applications. The GT	Original	PDF	AN-681 1e-15
Nelco 4000-13 Abstract: MEGTRON 6 370HR isola 370HR Nelco 4000-13 si Isola FR406 Rogers 4350B stackup 4000-13EP FR4 Prepreg Text: PCB Stackup Design Considerations for Altera FPGAs AN-613-1.0 Application Note This application note presents an overview of the PCB stackup construction and material selection criteria. It discusses the important material parameters that influence the electrical	Original	PDF	AN-613-1 Mil-Std-275E) Nelco 4000-13 MEGTRON 6 370HR isola 370HR Nelco 4000-13 si Isola FR406 Rogers 4350B stackup 4000-13EP FR4 Prepreg
he807 Abstract: he804 SOCAPEX HE804 YL 69 moisture HE801-HE807 socapex 127 H 17 HE804 connector HE804 amphenol amphenol HiLinX HE801 Text: Board Level Interconnect products Amphenol 2 "NQIFOPMt#PBSE-FWFM Interconnect products Table of Contents About Amphenol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4	Original	PDF	DOC-000090-ANG he807 he804 SOCAPEX HE804 YL 69 moisture HE801-HE807 socapex 127 H 17 HE804 connector HE804 amphenol amphenol HiLinX HE801
Board Level Abstract: AMPHENOL HE 508 amphenol HiLinX ute 93-424 Text: Board Level Interconnect products Amphenol 2 "NQIFOPMt#PBSE-FWFM Interconnect products Table of Contents About Amphenol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4	Original	PDF	DOC-000090-ANG Board Level AMPHENOL HE 508 amphenol HiLinX ute 93-424