Untitled
Abstract: No abstract text available
Text: PRELIMINARY |W|IC=RC3N 512K M T4C 8 512/3 L WIDE DRAM X 8 512K x 8 DRAM WIDE DRAM LOW POWER, EXTENDED REFRESH FEATURES PIN ASSIGNMENT Top View OPTIONS 28-Pin ZIP (DB-3) 28-Pin SOJ (DC-4) MARKING • Timing 60ns access 70ns access 80ns access • MASKED WRITE
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OCR Scan
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MT4C8513
024-cycle
128ms
350mW
28-Pin
MT4C8512/3
WT4C6512/3
S1993,
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PDF
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Untitled
Abstract: No abstract text available
Text: M T4C4003J lEG X 4 DRAM M IC R O N 1 MEG DRAM X 4 DRAM DRAM STATIC COLUMN FEATURES PIN ASSIGNMENT (Top View OPTIONS 20-Pin ZIP (DC-1) (DB-2) DQ1 DQ2 WE RAS A9 MARKING • Timing 70ns access 80ns access • Packages Plastic SOJ (300 mil) Plastic ZIP (350 mil)
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OCR Scan
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T4C4003J
024-cycle
20/26-Pin
20-Pin
MT4C4003J
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PDF
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Untitled
Abstract: No abstract text available
Text: • h ÉidMiuiilBHááttaSflÉ BflE D MICRON TECHNOLOGY INC b llIS H T G G O E Tll =i ■ MRN ADVANCE ÉtaB*6â*ù^ÂeeÂfcâi - uMMüff T4C-2Z-/< 16K X 16 SRAM SYNCHRONOUS SRAM W ITH CLOCKED, REGISTERED INPUTS FEATURES • • • • OPTIONS MARKING « Timing
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OCR Scan
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DQ12C
DQ13C
DQ14C
52-pin
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PDF
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Untitled
Abstract: No abstract text available
Text: MICRON B M T4C16256/7/8/9 L 256K X 16 WIDE DRAM BCMICDNDUCTaH. WC WIDE DRAM 256K x 16 DRAM LOW POWÉR, EXTENDED REFRESH FEATURES MARKING • T im ing 60ns access 70ns access 80ns access • W rite Cycle Access BYTE o r W ORD via WE nonm askable BYTE or W ORD via CAS
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OCR Scan
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T4C16256/7/8/9
T4C16257/9
T4C16258/9
512-cycle
500mW
40-Pin
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PDF
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Untitled
Abstract: No abstract text available
Text: ADVANCE MT4 L C2M8A1/2 2 MEG X 8 WIDE DRAM MICRON WIDE DRAM 2 MEG x 8 DRAM 5.0V, FAST-PAGE-MODE (MT4C2M8A1/2) 3.0/3.3V, FAST-PAGE-MODE (MT4LC2M8A1/2) FEATURES PIN ASSIGNMENT (Top View) OPTIONS MARKING • Timing 60ns access 70ns access 80ns access -6 -7 -8
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OCR Scan
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096-cycle
048-cycle
A0-A11;
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PDF
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MT8C
Abstract: No abstract text available
Text: M IC R O N MT8C9026 1MEG x 9 DRAM DRAM MODULE STATIC COLUMN PIN ASSIGNMENT (Top View OPTIONS MARKING • Timing 80ns access 100ns access 120ns access • Packages: Leaded 30 -pin SIP Leadless 30-pin SIMM -10 -12 MN M GENERAL DESCRIPTION The MT8C9026 is a randomly accessed solid-state
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OCR Scan
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MT8C9026
30-pin
1575mW
MT8C
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PDF
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Untitled
Abstract: No abstract text available
Text: ADVANCE MT4 L C2M8A1/2 2 MEG X 8 WIDE DRAM M IC R O N WIDE DRAM 2 MEG X 8 DRAM 5.0V, FAST-PAGE-MODE (MT4C2M8A1/2) 3.0/3.3V, FAST-PAGE-MODE (MT4LC2M8A1/2) FEATURES PIN ASSIGNMENT (Top View) OPTIONS MARKING • Timing 60ns access 70ns access 80ns access -6 -7
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OCR Scan
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28-Pin
28-pin
32-pin
A0-A11
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PDF
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Untitled
Abstract: No abstract text available
Text: ADVANCE MT4 L C2M8B1/2 S 2 MEG X 8 WIDE DRAM M ICRO N WIDE DRAM 2 MEG X 8 DRAM 5.0V SELF REFRESH ÍMT4C2M8B1/2 S) 3.0/3.3V, SELF REFRESH (MT4LC2M8B1/2 S) FEATURES PIN A SSIG N M EN T (Top View) OPTIONS MARKING • Timing 60ns access 70ns access 80ns access
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OCR Scan
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32-Pin
A0-A10;
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PDF
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Untitled
Abstract: No abstract text available
Text: ADVANCE M T4 L C 2M 8B 1/2 2 MEG X 8 W ID E DRAM I^ IIC R D N WIDE DRAM 2 MEG x 8 DRAM 5.0V FAST-PAGE-MODE (MT4C2M8B1/2) 3.0/3.3V, FAST-PAGE-MODE (MT4LC2M8B1/2) FEATURES PIN ASSIGNMENT (Top View) OPTIONS MARKING • Timing 60ns access 70ns access 80ns access
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OCR Scan
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048-cycle
096-cycle
400mW
A0-A10;
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PDF
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t3d01
Abstract: pin configuration of IC 1619 cp LM 3177 C16-256 MT4C16257
Text: PRELIMINARY M T 4C 16256/7/8/9 S 256K X 16 WIDE DRAM |U |I C R O N WIDE DRAM 2 5 6 K X 16 DRAM FAST-PAGE-MODE SELF REFRESH FEATURES OPTIONS P IN A S S IG N M E N T 4 0 -P in S O J T o p 4 0 -P in MARKING • Timing 70ns access -7 80ns access -8 • Write Cycle Access
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OCR Scan
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512-cycle
MT4C16257/9
MT4C16258/9
MT4C16256/7
MT4C16256/7/0/9
t3d01
pin configuration of IC 1619 cp
LM 3177
C16-256
MT4C16257
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PDF
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Untitled
Abstract: No abstract text available
Text: ADVANCE M T4C 1672 64K x 16 DRAM DRAM FAST PAGE MODE, DUAL CAS FEATURES • Industry standard xl6 pinouts, timing, functions and packages • High performance, CMOS silicon gate process • Single +5V±10% power supply • Low power, 3mW standby; 350mW active, typical
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OCR Scan
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350mW
256-cycle
100ns
400mil)
475mil)
40-Pin
DQ9-DQ16)
MT4C1672
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PDF
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Untitled
Abstract: No abstract text available
Text: ADVANCE M T4C 10016/7 16 MEG x1 DRAM FAST PAGE MODE: MT4C10016 STATIC COLUMN: MT4C10017 FEATURES • Industry standard xl pinout, timing, functions and packages • High performance, CMOS silicon gate process • Single power supply: +5V±10% or +3.3V±10%
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OCR Scan
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MT4C10016
MT4C10017
250mW
4096-cycle
475mil)
400mil)
MT4C10016/7
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PDF
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Untitled
Abstract: No abstract text available
Text: ADVANCE CZR M T4C 10016/7 16 MEG X 1 DRAM FAST PAGE MODE: MT4C10016 STATIC COLUMN: MT4C10017 FEATURES • Industry standard xl pinout, timing, functions and packages • High performance, CMOS silicon gate process • Single power supply: +5V±10% or +3.3V±10%
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OCR Scan
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MT4C10016
MT4C10017
250mW
4096-cycle
475mil)
400mil)
A0-A10/A11)
32ms/64ms,
MT4C10016/7
2048-cycle
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PDF
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Untitled
Abstract: No abstract text available
Text: ADVANCE M IC R O N M T4C40004/5 4 MEG x 4 DRAM FAST PAGE MODE: MT4C40004 STATIC COLUMN: MT4C40005 FEATURES • Industry standard x4 pinout, timing, functions and packages • High performance, CMOS silicon gate process • Single power supply : +5V±10% or +3.3V±10%
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OCR Scan
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T4C40004/5
250mW
2048-cycle
4096-cycle
475mil)
400mil)
MT4C40004/5
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PDF
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4C4256
Abstract: No abstract text available
Text: M T4C4256 L 256K X 4 DRAM |V |IC Z R O N DRAM 256K x 4 DRAM FEATURES • 512-cycle refresh in 8ms (MT4C4256) or 64ms (MT4C4256 L) • Industry-standard x4 pinout, tim ing, functions and packages • High-perform ance CM OS silicon-gate process • Single +5V +10% power supply
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OCR Scan
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T4C4256
512-cycle
MT4C4256)
MT4C4256
175mW
T4C4256L
20-Pin
4C4256
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PDF
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Untitled
Abstract: No abstract text available
Text: M T4C1006J MICRON I 4M E GX1 D R A M DRAM 4 MEG x 1 DRAM • FEATURES • Industry-standard x l pinout, timing, functions and packages • High-performance CMOS silicon-gate process • Single +5V ±10% power supply • Low power, 3mW standby; 225mW active, typical
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OCR Scan
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1006J
225mW
024-cycle
20/26-Pin
MT4C1006th
MT4C1006J
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PDF
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Untitled
Abstract: No abstract text available
Text: PRELIMINARY M T4C4M 4A1/B1 4 M EG X 4 DRAM v iic n o N DRAM 4 MEG X 4 DRAM FEATURES • Industry-standard x4 pinout, timing, functions and packages • High-performance CMOS silicon-gate process • Single power supply : +5V ±10% • Low pow'er, 3mW standby; 325mW active, typical (A l
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OCR Scan
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325mW
048-cycle
096-cycle
24-Pin
A0-A11
S1993,
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PDF
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1004J
Abstract: No abstract text available
Text: M T4C1004J L 4 MEG X 1 DRAM DRAM 4 MEG X 1 DRAM LOW POWER, EXTENDED REFRESH FEATURES • Industry standard x l pinout, timing, functions and packages • High-performance, CM OS silicon-gate process • Single +5V ±10% power supply • All inputs, outputs and clocks are fully TTL
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OCR Scan
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T4C1004J
024-cycle
128ms
225mW
20-Pin
MT4C1004JL
1004J
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PDF
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EDO DRAM
Abstract: MT4C4007JDJ-6L MT4C4007JDJ-6
Text: 1 MEG x 4 EDO DRAM V IIC Z R C H V S DRAM M T4C 4007J FEATURES PIN ASSIGNMENT (Top View Single+5V ±10% power supply JEDEC-standard pinout and packages High-performance CMOS silicon-gate process All inputs, outputs and clocks are TTL-compatible Refresh modes: RAS#-ONLY, CAS#-BEFORE- RAS#
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OCR Scan
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4007J
024-cycle
128ms
20/26-Pin
128ms
EDO DRAM
MT4C4007JDJ-6L
MT4C4007JDJ-6
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PDF
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MT4C1004
Abstract: No abstract text available
Text: M T4C1004J S 4 MEG X 1 DRAM (M IC R O N DRAM 4 MEG x 1 DRAM 5V, STANDARD OR SELF REFRESH • 1,024-cycle refresh distributed across 16ms (MT4C1004J) or 128ms (M T4C1004J S only) • Industry-standard pinout, tim ing, functions and packages • High-perform ance CM OS silicon-gate process
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OCR Scan
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T4C1004J
024-cycle
MT4C1004J)
128ms
MT4C1004J
20/26-Pin
MT4C1004
|
PDF
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Untitled
Abstract: No abstract text available
Text: M T 4 C 4 0 0 1 J S 1 MEG x 4 DRAM |U|(=RON DRAM 1 MEG x 4 DRAM 5V, STANDARD OR SELF REFRESH FEATURES • 1,024-cycle refresh distributed across 16ms (M T4C4001J) or 128ms (M T4C4001J S) • Industry-standard pinout, timing, functions and packages • High-perform ance CM OS silicon-gate process
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OCR Scan
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024-cycle
T4C4001J)
128ms
T4C4001J
MT4C4001J
20/26-Pin
MT4C4001
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PDF
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MT4C1004
Abstract: No abstract text available
Text: MT4C1004J S 4 MEG X 1 DRAM |U|K=RON DRAM 4 MEG X 1 DRAM FEATURES • 1,024-cycle refresh distributed across 16ms (M T4C1004J) or 128ms (MT4C1004J S only) • Industry-standard pinout, tim ing, functions and packages • High-perform ance CM OS silicon-gate process
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OCR Scan
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MT4C1004J
024-cycle
T4C1004J)
128ms
T4C1004J
20/26-Pin
20-Pin
MT4C1004
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PDF
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T4C16257DJ
Abstract: t4c16257 T4C16257DJ-7
Text: l^ lld R O N 256K DRAM M T4C 16257 X 16 DRAM 256K x 16 DRAM 5V, FAST PAGE MODE • Industry-standard x l6 pinouts, timing, functions and packages • High-perform ance CM OS silicon-gate process • Single +5V ±10% power supply* • Low power, 3m W standby; 375m W active, typical
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OCR Scan
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512-cycle
40-Pin
40/44-Pin
MT4C16257
T4C16257DJ
t4c16257
T4C16257DJ-7
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PDF
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Untitled
Abstract: No abstract text available
Text: M ’ I C R O N 1 MEG X 1 FPM D R A M DRAM M T4C 1004J FEATURES • 1,024-cycle refresh distributed across 16ms M T4C1004J or 128ms (M T4C1004J L only) • Industry-standard pinout, tim ing, functions and packages • High-perform ance CM OS silicon-gate process
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OCR Scan
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024-cycle
T4C1004J)
128ms
T4C1004J
1004J
20/26-Pin
A10CL
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PDF
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