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    Untitled

    Abstract: No abstract text available
    Text: fZ J 7 # ^ M48Z512 M48Z512Y S C S -T H O M S O N RiflQMSEILKOTORQDÊi CMOS 512K X 8 ZEROPOWER SRAM PRELIMINARY DATA • INTEGRATED LOW POWER SRAM, POWER­ FUL CONTROL CIRCUIT AND BATTERY ■ CONVENTIONAL SRAM OPERATION; UN­ LIMITED WRITE CYCLES ■ 5 YEAR MINIMUM DATA RETENTION IN THE


    OCR Scan     		PDF M48Z512 M48Z512Y M48Z512 M48Z512/512Y M48Z512, M48K512Y PMLDIP32

    si977

    Abstract: 48Z512Y
    Text: /=7 SGS-TtfOMSON ^ 7 # M 48Z512 M 48Z512Y M ^ © iL [i g ? ^ (Q iO (g S CMOS 512K X 8 ZEROPOWER SRAM PRELIMINARY DATA • INTEGRATED LOW POWER SRAM, POWERFAIL CO N TRO L CIRCUIT AND BATTERY ■ C O N V E N T IO N A L SRAM O P E R A T IO N ; UN­ LIMITED W RITE CYC LES


    OCR Scan     		PDF 48Z512 48Z512Y 48Z512Y M48Z512, M48K512Y M48Z512 LDIP32 si977