LVDCI25
Abstract: LVDCI18 HSTL_
Text: R Digitally Controlled Impedance DCI LVCMOS25 Table 2-66 lists DC voltage specifications. Table 2-66: LVCMOS25 Voltage Specifications Parameter Min Typ Max VCCO 2.3 2.5 2.7 VREF - - - VTT - - - VIH 1.7 - 2.7 VIL −0.5 - 0.7 VOH 1.9 - - VOL - - 0.4 IOH at VOH (mA)
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LVCMOS25
LVCMOS25
LVCMOS33
LVCMOS33
UG012
LVDCI25
LVDCI18
HSTL_
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4032V
Abstract: DS1017 LC4032V-10TN48I 4512c application LC4256V-75TN176C marking 17Z 4000B AEC-Q100 DS1020 22z2
Text: ispMACH 4000V/B/C/Z Family 3.3V/2.5V/1.8V In-System Programmable SuperFAST TM High Density PLDs Coolest Power May 2009 C Features Data Sheet DS1020 TM • Broad Device Offering • Multiple temperature range support – Commercial: 0 to 90°C junction Tj
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000V/B/C/Z
DS1020
AEC-Q100
000V/Z
400MHz
nonAEC-Q100
256-ftBGA
4A-07.
4000Z
000V/B/C
4032V
DS1017
LC4032V-10TN48I
4512c application
LC4256V-75TN176C
marking 17Z
4000B
DS1020
22z2
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XC3S700A
Abstract: xc3s200aft256 XC3S400AFT256 XC3S50A L01P L02P FG320 UG331 L05P xc3s400a ftg256
Text: Spartan-3A FPGA Family: Data Sheet R DS529 July 10, 2007 Product Specification Module 1: Introduction and Ordering Information - DS529-1 v1.4.1 July 10, 2007 • • • • • • • Introduction Features Architectural and Configuration Overview General I/O Capabilities
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DS529
DS529-1
DS529-2
DS529-3
XC3S50A
XC3S200A
FT256
DS529-4
XC3S700A
xc3s200aft256
XC3S400AFT256
L01P
L02P
FG320
UG331
L05P
xc3s400a ftg256
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AFS600-FG256
Abstract: zo 103 ma 75 607 A54 ZENER flashpro3 schematic mark AT0 Unipolar PC atx 400 P4 power supply diagram zener Diode B23 PQ208 QN108 QN180
Text: Preliminary v1.7 Actel Fusion Mixed-Signal FPGAs Family with Optional ARM® Support Features and Benefits – Frequency: Input 1.5–350 MHz, Output 0.75–350 MHz Low Power Consumption High-Performance Reprogrammable Flash Technology • • • • • Single 3.3 V Power Supply with On-Chip 1.5 V Regulator
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130-nm,
128-Bit
AFS600-FG256
zo 103 ma 75 607
A54 ZENER
flashpro3 schematic
mark AT0
Unipolar PC atx 400 P4 power supply diagram
zener Diode B23
PQ208
QN108
QN180
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MachXO sysIO Usage Guide
Abstract: LCMXO256C-4M100C LCMXO2280 lcmxo640c-3tn100i LCMXO640C-3FT256C LCMXO1200 LCMXO256 LCMXO2280E-4M132I LVCMOS15 LVCMOS25
Text: MachXO Family Data Sheet Version 02.3_4W February 2007 MachXO Family Data Sheet Introduction April 2006 Data Sheet • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 − LVTTL
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TN1086)
TN1087)
TN1097)
MachXO sysIO Usage Guide
LCMXO256C-4M100C
LCMXO2280
lcmxo640c-3tn100i
LCMXO640C-3FT256C
LCMXO1200
LCMXO256
LCMXO2280E-4M132I
LVCMOS15
LVCMOS25
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Untitled
Abstract: No abstract text available
Text: iCE40 LP/HX Family Data Sheet DS1040 Version 02.9, April 2014 iCE40 LP/HX Family Data Sheet Introduction February 2014 Data Sheet DS1040 Features Flexible Logic Architecture – Schmitt trigger inputs, to 200 mV typical hysteresis • Programmable pull-up mode
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iCE40â
DS1040
iCE40
DS1040
LP384
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Untitled
Abstract: No abstract text available
Text: Artix-7 FPGAs Data Sheet: DC and Switching Characteristics DS181 v1.6 April 17, 2013 Product Specification Introduction Artix -7 FPGAs are available in -3, -2, -1, and -2L speed grades, with -3 having the highest performance. The -2L devices can operate at either of two VCCINT voltages, 0.9V
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DS181
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Untitled
Abstract: No abstract text available
Text: Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics DS183 v1.18 November 26, 2013 Product Specification Introduction Virtex -7 T and XT FPGAs are available in -3, -2, -1, and -2L speed grades, with -3 having the highest performance.
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DS183
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A54 ZENER
Abstract: AFS600-FG256 mark AT0 QN108 CORE8051 bipolar ROM
Text: v2.0 Actel Fusion Family of Mixed-Signal FPGAs Features and Benefits In-System Programming ISP and Security High-Performance Reprogrammable Flash Technology Advanced Digital I/O • • • • • Secure ISP with 128-Bit AES via JTAG • FlashLock® to Secure FPGA Contents
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128-Bit
130-nm,
A54 ZENER
AFS600-FG256
mark AT0
QN108
CORE8051
bipolar ROM
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UG628
Abstract: No abstract text available
Text: Spartan-6 FPGA Configuration User Guide UG380 v2.5 January 23, 2013 Notice of Disclaimer The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL
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UG380
UG628
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4032 k14
Abstract: 4512c PX6A10 4256b L5591 a/4032 k14 am 4512C LC45 4064C m6 pt80
Text: TM ispMACH 4000B/C Family 2.5V/1.8V In-System Programmable SuperFAST TM High Density PLDs December 2001 Data Sheet • Broad Device Offering Features • • • • ■ High Performance • fMAX = 350MHz maximum operating frequency • tPD = 2.5ns propagation delay
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4000B/C
350MHz
4000B)
4000C)
LC4512C-5F256I
LC4512C-75F256I
LC4512C-10F256I
TN1004)
4032 k14
4512c
PX6A10
4256b
L5591
a/4032 k14
am 4512C
LC45
4064C
m6 pt80
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lfxp2-40e
Abstract: LVCMOS25 LD48 LFXP2-17E-5FTN256C HB1004 ispLEVER project Navigator route place LFXP2-5E-5QN IPUG35 LFXP2-8E
Text: LatticeXP2 Family Handbook HB1004 Version 02.9, May 2011 LatticeXP2 Family Handbook Table of Contents May 2011 Section I. LatticeXP2 Family Data Sheet Introduction Features . 1-1
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HB1004
TN1144
TN1220.
TN1143
lfxp2-40e
LVCMOS25
LD48
LFXP2-17E-5FTN256C
ispLEVER project Navigator route place
LFXP2-5E-5QN
IPUG35
LFXP2-8E
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XAPP393
Abstract: DS090 VQ100 XC2C128 XC2C256 XC2C32 XC2C384 XC2C64 interfacing 8051 XC9500 cpld pins table
Text: R CoolRunner-II CPLD Family DS090 v1.7 October 2, 2003 Preliminary Product Specification Features • • • • Optimized for 1.8V systems - Industry’s fastest low power CPLD - Static Icc of less than 100 microamps at all times - Densities from 32 to 512 macrocells
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DS090
IEEE1149
f/wp170
XAPP393
DS090
VQ100
XC2C128
XC2C256
XC2C32
XC2C384
XC2C64
interfacing 8051 XC9500
cpld pins table
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SPARTAN-3 XC3S400 PQ208
Abstract: SPARTAN-3 XC3S400 pq208 architecture SPARTAN-3 XC3S400 tq144 SPARTAN-3 XC3S400 Spartan-3 FPGA Family XC3S4000-FG676 SPARTAN-3 XC3S400 pin SPARTAN-3 XC3S400 architecture XC3S4000FG676 XILINX SPARTAN VQG100
Text: 06 Spartan-3 FPGA Family: Introduction and Ordering Information R DS099-1 v1.4 January 17, 2005 Preliminary Product Specification Introduction - The Spartan -3 family of Field-Programmable Gate Arrays is specifically designed to meet the needs of high volume,
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DS099-1
XC3S50CP132,
XC3S2000FG456,
XC3S4000FG676
DS099-1,
DS099-2,
DS099-3,
DS099-4,
DS313,
DS314-1,
SPARTAN-3 XC3S400 PQ208
SPARTAN-3 XC3S400 pq208 architecture
SPARTAN-3 XC3S400 tq144
SPARTAN-3 XC3S400
Spartan-3 FPGA Family
XC3S4000-FG676
SPARTAN-3 XC3S400 pin
SPARTAN-3 XC3S400 architecture
XILINX SPARTAN VQG100
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XQ4VSX55
Abstract: xq4vlx25 XQ4VLX60-10FF668M XQ4VLX40 XQ4VFX60 xq4vlx60 XQ4VFX60-10EF672M XQ4VLX40-10FF668M XQ4VLX100 Virtex 4Q
Text: Virtex-4Q FPGA Data Sheet: DC and Switching Characteristics R DS595 v1.6 April 27, 2010 Product Specification Virtex-4Q FPGA Electrical Characteristics Defense-grade Virtex -4Q FPGAs are available in -10 speed grade and are qualified for industrial (TJ = –40°C to +100°C),
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DS595
XQ4VSX55
xq4vlx25
XQ4VLX60-10FF668M
XQ4VLX40
XQ4VFX60
xq4vlx60
XQ4VFX60-10EF672M
XQ4VLX40-10FF668M
XQ4VLX100
Virtex 4Q
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XCF00S
Abstract: automotive ecu automotive ecu circuit LVDSEXT-25 AEC-Q100 TS16949 VQG100 LVDSEXT25 BLVDS-25
Text: 06 Spartan-3 Automotive XA FPGA Family: Introduction and Ordering R DS314-1 v1.0 October 18, 2004 Advance Product Specification Introduction The Xilinx Automotive (XA) Spartan -3 family of Field-Programmable Gate Arrays is specifically designed to meet the
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DS314-1
AEC-Q100
DS099-1,
DS099-2,
DS099-3,
DS099-4,
XCF00S
automotive ecu
automotive ecu circuit
LVDSEXT-25
TS16949
VQG100
LVDSEXT25
BLVDS-25
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COOLRUNNER-II examples
Abstract: XA CoolRunner-II XAPP393 VQG44 CoolRunner-II CPLD AEC-Q100 TS16949 XA2C128 XA2C256 XA2C32A
Text: CoolRunner-II CPLD XA Product Family R DS315-1 v1.0 October 18, 2004 Advance Product Specification Features • • • • • AEC-Q100 device qualification and full PPAP support available in both extended temperature Q-grade and I-grade. Optimized for 1.8V systems
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DS315-1
AEC-Q100
IEEE1149
com/bvdocs/publications/ds095
XC2C384
com/bvdocs/publications/ds096
XC2C512
com/bvdocs/whitepapers/wp165
com/bvdocs/whitepapers/wp170
COOLRUNNER-II examples
XA CoolRunner-II
XAPP393
VQG44
CoolRunner-II CPLD
TS16949
XA2C128
XA2C256
XA2C32A
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XC3S700AN FGG484
Abstract: XC3S400AN-FGG400 XC3S700A FGG484 xc3s200an XC3S400AN FGG400 FGG676 SPARTAN 3an XC3S50A XC3S700AN-FG484 XC3S700AN
Text: Spartan-3AN FPGA Family Data Sheet R DS557 June 2, 2008 Module 1: Introduction and Ordering Information - DS557-1 v3.1 June 2, 2008 • • • • • • • • Introduction Features Architectural Overview Configuration Overview In-system Flash Memory Overview
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DS557
DS557-1
XC3S50AN.
XC3S700AN
FG484
XC3S1400AN
FGG676
DS557-4
XC3S700AN FGG484
XC3S400AN-FGG400
XC3S700A FGG484
xc3s200an
XC3S400AN
FGG400
SPARTAN 3an
XC3S50A XC3S700AN-FG484
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LVDSEXT-25
Abstract: 16x1D LVPECL33 16X1S LVDS-25 LVDS-33 LVDSEXT25 LVDCI18 LVDCI25 LVDS25
Text: Virtex-II 1.5V Field-Programmable Gate Arrays R DS031-2 v1.9 November 29, 2001 Advance Product Specification Detailed Description Input/Output Blocks (IOBs) Table 1: Supported Single-Ended I/O Standards Virtex-II I/O blocks (IOBs) are provided in groups of two or
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DS031-2
LVCMOS33
LVCMOS25
DS031-1,
DS031-3,
DS031-4,
DS031-2,
LVDSEXT-25
16x1D
LVPECL33
16X1S
LVDS-25
LVDS-33
LVDSEXT25
LVDCI18
LVDCI25
LVDS25
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UG366
Abstract: LX760
Text: Virtex-6 FPGA Data Sheet: DC and Switching Characteristics DS152 v3.5 May 17, 2013 Product Specification Virtex-6 FPGA Electrical Characteristics Virtex -6 FPGAs are available in -3, -2, -1, and -1L speed grades, with -3 having the highest performance. Virtex-6 FPGA
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DS152
UG366
LX760
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LCMXO2-1200HC-4TG100C
Abstract: LCMXO2-256HC-4TG100I LCMXO2-1200 tn1200 lcmxo2 LCMXO2-1200HC-4TG100 LCMXO2-2000 LCMXO2-7000 MachXO2-1200 LCMXO2-4000HC
Text: MachXO2 Family Handbook HB1010 Version 01.0, November 2010 MachXO2 Family Handbook Table of Contents November 2010 Section I. MachXO2 Family Data Sheet Introduction Features . 1-1
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HB1010
LCMXO2-1200HC-4TG100C
LCMXO2-256HC-4TG100I
LCMXO2-1200
tn1200
lcmxo2
LCMXO2-1200HC-4TG100
LCMXO2-2000
LCMXO2-7000
MachXO2-1200
LCMXO2-4000HC
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TPE11
Abstract: TPT20 CON6A v2 tpr4 pr48b PT13B condor E5 Condor LVCMOS15 LVCMOS25
Text: LatticeEC Standard Evaluation Board – Revision B User’s Guide April 2007 ebug10_01.4 Lattice Semiconductor LatticeEC Standard Evaluation Board – Revision B User’s Guide Introduction The LatticeEC Standard Evaluation Board provides a convenient platform to evaluate, test and debug user
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ebug10
120-pin)
32-bit
PVG5H503A01
TPE11
TPT20
CON6A
v2 tpr4
pr48b
PT13B
condor E5
Condor
LVCMOS15
LVCMOS25
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LVCMOS25
Abstract: LVCMOS15 LVCMOS33 LVCMOS18 ECP2M date sheet of ninth class
Text: LatticeECP2/M sysIO Usage Guide June 2010 Technical Note TN1102 Introduction The LatticeECP2 and LatticeECP2M™ sysIO™ buffers give the designer the ability to easily interface with other devices using advanced system I/O standards. This technical note describes the sysIO standards available and
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TN1102
LVCMOS25
LVCMOS15
LVCMOS33
LVCMOS18
ECP2M
date sheet of ninth class
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TN1178
Abstract: DDR3 DIMM footprint LVCMOS15 LVCMOS25 LVCMOS33 SSTL15D k2xsc
Text: LatticeECP3 High-Speed I/O Interface June 2010 Technical Note TN1180 Introduction LatticeECP3 devices support high-speed I/O interfaces, including Double Data Rate DDR and Single Data Rate (SDR) interfaces, using the logic built into the Programmable I/O (PIO). SDR applications capture data on one
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TN1180
TN1178
DDR3 DIMM footprint
LVCMOS15
LVCMOS25
LVCMOS33
SSTL15D
k2xsc
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