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    GATE AND PAL ARCHITECT Search Results

    GATE AND PAL ARCHITECT Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TB67H481FTG Toshiba Electronic Devices & Storage Corporation Stepping and Brushed Motor Driver /Bipolar Type / Vout(V)=50 / Iout(A)=3.0 / IN input type / VQFN32 Visit Toshiba Electronic Devices & Storage Corporation
    TLP5702H Toshiba Electronic Devices & Storage Corporation Photocoupler (Gate Driver Coupler), High-Topr / IGBT driver, 5000 Vrms, SO6L Visit Toshiba Electronic Devices & Storage Corporation
    TLP5705H Toshiba Electronic Devices & Storage Corporation Photocoupler (Gate Driver Coupler), High-Topr / IGBT driver, 5000 Vrms, SO6L Visit Toshiba Electronic Devices & Storage Corporation
    7UL2T125FK Toshiba Electronic Devices & Storage Corporation One-Gate Logic(L-MOS), Buffer, SOT-765 (US8), -40 to 85 degC Visit Toshiba Electronic Devices & Storage Corporation
    7UL2T126FK Toshiba Electronic Devices & Storage Corporation One-Gate Logic(L-MOS), Buffer, SOT-765 (US8), -40 to 85 degC Visit Toshiba Electronic Devices & Storage Corporation

    GATE AND PAL ARCHITECT Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    EPM5130

    Abstract: max 5000
    Text: MAX 5000 Programmable Logic Device Family May 1999, ver. 5 Features. Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ Advanced Multiple Array MatriX MAX® 5000 architecture combining speed and ease-of-use of PAL devices with the density of programmable gate arrays


    Original     		28-pin 100-pin 15-ns 84-Pin EPM5192 EPM5130 max 5000 PDF

    Untitled

    Abstract: No abstract text available
    Text: MAX 5000 Programmable Logic Device Family January 1998, ver. 4 Features. Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ Advanced Multiple Array MatriX MAX® 5000 architecture combining speed and ease-of-use of PAL devices with the density of programmable gate arrays


    Original     		28-pin 100-pin 15-ns EPM5192 84-Pin PDF

    EPM5128GM

    Abstract: EPM5128GC EPM5128JC EPM5032DC EPM5128GC-1 epm5130qc EPM5130QC-2 EPM5032DC-20 EPM5032DC-15 EPM5130LC
    Text: MAX 5000 Programmable Logic Device Family May 1999, ver. 5 Features. Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ Advanced Multiple Array MatriX MAX® 5000 architecture combining speed and ease-of-use of PAL devices with the density of programmable gate arrays


    Original     		28-pin 100-pin 15-ns EPM5032PC-17 EPM5032SC-15 EPM5032SC-17 EPM5032SC-20 EPM5032SC-25 EPM5032SC-15, EPM5128GM EPM5128GC EPM5128JC EPM5032DC EPM5128GC-1 epm5130qc EPM5130QC-2 EPM5032DC-20 EPM5032DC-15 EPM5130LC PDF

    EPM5130

    Abstract: EPM5192 EPM5064 EPM5032 EPM5032-15 EPM5064-1 EPM5128 ALTERA MAX 5000 EPM5064-2 ALTERA MAX 5000 programming
    Text: MAX 5000 Programmable Logic Device Family June 1996, ver. 3 Features. Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ Advanced Multiple Array MatriX MAX 5000 architecture combining speed and ease-of-use of PAL devices with the density of programmable gate arrays


    Original     		28-pin 100-pin 15-ns EPM5192 84-Pin EPM5130 EPM5192 EPM5064 EPM5032 EPM5032-15 EPM5064-1 EPM5128 ALTERA MAX 5000 EPM5064-2 ALTERA MAX 5000 programming PDF

    EPM5130

    Abstract: L9116 EPM5064 EPM5032 EPM5032-15 EPM5064-1 EPM5128 EPM5192 epm5130g EPM5032-2
    Text: MAX 5000 Programmable Logic Device Family June 1996, ver. 3 Features. Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ Advanced Multiple Array MatriX MAX 5000 architecture combining speed and ease-of-use of PAL devices with the density of programmable gate arrays


    Original     		28-pin 100-pin 15-ns EPM5192 84-Pin EPM5130 L9116 EPM5064 EPM5032 EPM5032-15 EPM5064-1 EPM5128 EPM5192 epm5130g EPM5032-2 PDF

    Untitled

    Abstract: No abstract text available
    Text: MACH 5 Timing Considerations Application Note by Kristin Ahrens INTRODUCTION The MACH 5 Architecture provides predictably fast logic at high-density, and also provides some unique and advanced clocking features. The timing characteristics outlined in this application note are analogous to


    Original     		PDF

    Untitled

    Abstract: No abstract text available
    Text: Application Notes MACH 5 Timing Considerations INTRODUCTION The MACH 5 Architecture provides predictably fast logic at high-density, and also provides some unique and advanced clocking features. The timing characteristics outlined in this application note


    Original     		PDF

    TEA 1045

    Abstract: mach211sp
    Text: MACH 5 FAMILY 1 ADVANCE INFORMATION COM’L: -5/7/10/12 IND: -7/10/12/15 MACH5LV-128 MACH5LV-128/68-5/7/10/12 MACH5LV-128/104-5/7/10/12 MACH5LV-128/120-5/7/10/12 Fifth Generation MACH Architecture DISTINCTIVE CHARACTERISTICS ◆ Pin-, function- and JEDEC-compatible with the MACH5-128


    Original     		MACH5LV-128 MACH5LV-128/68-5/7/10/12 MACH5LV-128/104-5/7/10/12 MACH5LV-128/120-5/7/10/12 MACH5-128 MACH5LV-128/XXX-7/10/12/15 TEA 1045 mach211sp PDF

    Untitled

    Abstract: No abstract text available
    Text: MACH 5 FAMILY 1 ADVANCE INFORMATION COM’L: -5/7/10/12 IND:-7/10/12/15 MACH5LV-192 MACH5LV-192/68-5/7/10/12 MACH5LV-192/160-5/7/10/12 MACH5LV-192/104-5/7/10/12 MACH5LV-192/120-5/7/10/12 Fifth Generation MACH Architecture DISTINCTIVE CHARACTERISTICS ◆ Pin-, function- and JEDEC-compatible with the MACH5-192


    Original     		MACH5LV-192 MACH5LV-192/68-5/7/10/12 MACH5LV-192/160-5/7/10/12 MACH5LV-192/104-5/7/10/12 MACH5LV-192/120-5/7/10/12 MACH5-192 MACH5LV-192/XXX-7/10/12/15 PDF

    TEA 1045

    Abstract: MACH5LV
    Text: MACH 5 FAMILY 1 ADVANCE INFORMATION COM’L: -5/7/10/12 IND: -7/10/12/15 MACH5LV-256 MACH5LV-256/68-5/7/10/12 MACH5LV-256/120-5/7/10/12 MACH5LV-256/104-5/7/10/12 MACH5LV-256/160-5/7/10/12 Fifth Generation MACH Architecture DISTINCTIVE CHARACTERISTICS ◆ Pin-, function- and JEDEC-compatible with the MACH5-256


    Original     		MACH5LV-256 MACH5LV-256/68-5/7/10/12 MACH5LV-256/120-5/7/10/12 MACH5LV-256/104-5/7/10/12 MACH5LV-256/160-5/7/10/12 MACH5-256 MACH5LV-256/XXX-7/10/12/15 TEA 1045 MACH5LV PDF

    "XOR Gate"

    Abstract: Applications of "XOR Gate" XAPP313 XOR GATE CoolRunner data sheet for 3 input xor gate MC19 XCR960 SIGNAL PATH designer
    Text: Application Note: CoolRunner CPLD tri-state Achieving High Performance in a CoolRunner™ XCR3960 R XAPP313 v1.0 October 22, 1999 Application Note Local ZIA Local ZIA Local ZIA Figure 1 shows a representation of the XCR3960 architecture. The XCR3960 consists of 12


    Original     		XCR3960 XAPP313 XCR3960 NX5406. nx5406) nx5406 "XOR Gate" Applications of "XOR Gate" XAPP313 XOR GATE CoolRunner data sheet for 3 input xor gate MC19 XCR960 SIGNAL PATH designer PDF

    EPM5130

    Abstract: No abstract text available
    Text: MAX 5000 Programmable Logic Device Family January 1998. ver. 4 Features. Data Sheet • ■ ■ ■ ■ ■ ■ ■ Advanced Multiple Array M atrix MAX® 5000 architecture combining speed and ease-of-use of PAL devices with the density of programmable gate arrays


    OCR Scan     		28-pin 100-pin 15-ns EPM5130 PDF

    Untitled

    Abstract: No abstract text available
    Text: MAX 5000 Programmable Logic Device Family June 1996, ver. 3 F e a tu re s. Data Sheet * • ■ ■ ■ ■ ■ ■ ■ Advanced Multiple Array Matrix MAX 5000 architecture combining speed and ease-of-use of PAL devices with the density of programmable gate arrays


    OCR Scan     		28-pin 100-pin 15-ns 84-Pin 000500b PDF

    epm5064

    Abstract: EPM5130 EPM5128 APPLICATION NOTE CERAMIC CHIP CARRIER LCC 68 socket EPM5130 adapter
    Text: MAX 5000 Programmable Logic Device Family May 1999, ver. 5 F e a tu r e s. Data Sheet * • ■ ■ ■ ■ ■ ■ ■ Advanced Multiple Array Matrix MAX 5000 architecture combining speed and ease-of-use of PAL devices with the density of programmable gate arrays


    OCR Scan     		28-pin 100-pin 15-ns 84-Pin EPM5192 epm5064 EPM5130 EPM5128 APPLICATION NOTE CERAMIC CHIP CARRIER LCC 68 socket EPM5130 adapter PDF

    Untitled

    Abstract: No abstract text available
    Text: ACT 3 3.3 Volt Field Programmable Gate Arrays F eatu res • 3.3V Functionality specifications fully compliant with JEDEC Replaces up to 250 TTL Packages Replaces up to 100 20-pin PAL Packages • Highly Predictable Performance with 100% Automatic Placement and Routing


    OCR Scan     		20-pin PDF

    EPM5130

    Abstract: program EPM5032
    Text: MAX 5000 M UM Programmable Logic Device Family May 1999. ver. Features. • ■ ■ ■ ■ ■ ■ ■ Advanced M ultiple A rray M atriX MAX® 5000 architecture com bining speed and ease-of-use of PAL devices w ith the density of program m able gate arrays


    OCR Scan     		28-pin 100-pin 15-ns 84-Pin EPM5192 EPM5130 program EPM5032 PDF

    Untitled

    Abstract: No abstract text available
    Text: Æ tctel - w ACT 1 Series FPGAs Features • 5V and 3.3V Families fully compatible with JEDEC specifications • Up to 2000 Gate Array Gates 6000 PLD equivalent gates • Replaces up to 50 TTL Packages • Replaces up to twenty 20-Pin PAL Packages


    OCR Scan     		20-Pin A1010B A10V10B A1020B A10V20B IL-STD-883 A1010 PDF

    J-Lead, QFP ceramic

    Abstract: IC 7400 SERIES book EPM 5192
    Text: M A X 5000 Programmable Logic Device Family March 1995, ver. 2 Features. D a ta she et • ■ ■ ■ ■ ■ ■ Advanced M ultiple Array M atrix MAX 5000 architecture com bining speed and ease-of-use of PAL devices w ith density of program m able gate arrays


    OCR Scan     		28-pin 100-pin 10-ns 125-MHz J-Lead, QFP ceramic IC 7400 SERIES book EPM 5192 PDF

    Untitled

    Abstract: No abstract text available
    Text: ACT 1 and A C T 2 Military Field P rogram m able G ate Arrays ACT 1 Features ACT 2 Features • Up to 2000 Gate Array Gates 6000 PLD/LCA™ equivalent gates • Replaces up to 53 TTL Packages • Replaces up to 17 20-Pin PAL Packages • Design Library with over 250 Macros


    OCR Scan     		20-Pin PDF

    A1010APG84B

    Abstract: A1280Acq
    Text: ACT 1 and ACT 2 Military Field Programmable Gate Arrays ACT 1 Features ACT 2 Features • * U p to 2000 G ate A rray G ates 6000 PL D eq u iv alen t gates • R eplaces up to 53 T T L P ackages • R eplaces up to seventeen 20-P in PAL Packages •


    OCR Scan     		20-Pin 172-Pin A1010APG84B A1280Acq PDF

    TIBPAL22V

    Abstract: No abstract text available
    Text: P R O G R A M M A B L E LOGIC Introduction Texas Instruments Military Products is committed to meeting your system requirement needs for programmable logic. Tl offers a variety of programmable logic devices to help bridge the gap between S S I/ M S I and LSI/Gate A rrays in military designs. With a single PAL 1C from


    OCR Scan     		PDF

    Untitled

    Abstract: No abstract text available
    Text: ADVANCE INFORMATION COM 'L:-5/7/10/12 IND:-7/10/12/15 MACH5LV-192 V A N T I A N A M D S C O M P A N Y MACH51AM 9 2 /6 8 -5 /7 /1 0 /1 2 M ACH5LV-192/16 0 -5 /7 /1 0 /1 2 ; MACH5LV-19 2 /1 0 4 -5 /7 /1 0 /1 2 MACH5LV-192/1 2 0 -5 /7 /1 0 /1 2 Fifth Generation MACH Architecture


    OCR Scan     		MACH5LV-192 MACH51AM ACH5LV-192/16 MACH5LV-19 MACH5LV-192/1 MACH5LV-192/XXX-7/10/12/15 PDF

    Untitled

    Abstract: No abstract text available
    Text: PRELIMINARY AMDB The MACH 5 Family Fifth Generation MACH Architecture DISTINCTIVE CHARACTERISTICS • Fifth generation MACH architecture — 100% routable — Pin-out retention — Four power/speed options per block for maximum performance and lowest power


    OCR Scan     		PDF

    MACH5LV

    Abstract: No abstract text available
    Text: ADVANCE INFORMATION COM'L: -5/7/10/12 IND: -7/10/12/15 MACH5LV-256 V A N A N A M D T I S C O M P A N Y M A C H 5LV -256/68-5/7/10 /1 2 M ACH5LV-256/12 0 -5 /7 /1 0 /1 2 M ACHSLV-256/104-5/7 /1 0 /1 2 MACH5LV-2 56/16 0 -5 /7 /1 0 /1 2 Fifth Generation MACH Architecture


    OCR Scan     		MACH5LV-256 ACH5LV-256/12 ACHSLV-256/104-5/7 MACH5-256 MACH5LV-256/XXX-7/10/12/15 MACH5LV PDF