AL460A
Abstract: AL460A-7 25X2 AL460A-13-EVB-A0 al460 LP3852 MALE PIN HEADER 25X2
Text: AL460A HD-FIFO EVB Flyer AL460A HD-FIFO Evaluation Board Fulfill your FIFO potential! High-Speed First-In-First-Out memory buffer for HD Video applications AL460A HD-FIFO Advantages Introduction This EVB board is designed for evaluating the AL460A HD-FIFO integrated chip. It has two
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AL460A
AL460A-7
32-bits.
50-pin
32-bit
x32-bit
25X2
AL460A-13-EVB-A0
al460
LP3852
MALE PIN HEADER 25X2
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TQFP 100 PACKAGE footprint
Abstract: TQFP 144 PACKAGE footprint bga 208 PACKAGE 144-BB BGA and QFP Package 256X8 208 BGA 72V3613 BI 7284 footprint tqfp 208
Text: Selector Guide for 6WDQGDUG 6WDQGDUG ,)2 ),)2 Products From IDT, the leading provider of FIFO solutions Standard Standard FIFO FIFO Products Products ¾ ¾ ¾ ¾ ¾ FIFO Quick Reference Guide ……………………… Featured Product: TeraSync FIFO Family ……….
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TL16C554N
Abstract: XR16C854CVF XR16C854IV DAN108
Text: XR16C854 -Quad UART with RX/TX FIFO Counters and 128-Byte FIFO HomeNewsCareers Investor Relations Contact Us PartnerNet Login Search CommunicationsInterfacePower Management XR16C854 Support Info Request How to Order Samples Print this page Quad UART with RX/TX FIFO Counters and 128-Byte FIFO
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XR16C854
128-Byte
TL16C554N
XR16C854CVF
XR16C854IV
DAN108
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dcfifo
Abstract: asynchronous fifo vhdl altera MTBF dcfifo_mixed_widths
Text: SCFIFO and DCFIFO Megafunctions UG-MFNALT_FIFO-6.2 User Guide Altera provides FIFO functions through the parameterizable single-clock FIFO SCFIFO and dual-clock FIFO (DCFIFO) megafunctions. The FIFO functions are mostly applied in data buffering applications that comply with the first-in-first-out
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Untitled
Abstract: No abstract text available
Text: Document No.: FT_000052 FT245R USB FIFO IC Datasheet Version 2.03 Clearance No.: FTDI# 39 Future Technology Devices International Ltd. FT245R USB FIFO IC The FT245R is a USB to parallel FIFO interface with the following advanced features: • Single chip USB to parallel FIFO bidirectional
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FT245R
500uA
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zilog SCC sdlc software
Abstract: IN SDLC PROTOCOL WR10 Z85230 Z85233
Text: EMSCC Enhanced Mono Serial Communication Controller Z85233 Product Brief PB005802-0608 FEATURES • Hardware and software compatible with Zilog's SCC/ ESCC™ • Deeper Data FIFOs – 4-Byte Transmit FIFO – 8-Byte Receive FIFO • Programmable FIFO Interrupt Levels Provide
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Z85233
PB005802-0608
zilog SCC sdlc software
IN SDLC PROTOCOL
WR10
Z85230
Z85233
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FT245R
Abstract: No abstract text available
Text: Document No.: FT_000052 FT245R USB FIFO IC Datasheet Version 2.13 Clearance No.: FTDI# 39 Future Technology Devices International Ltd. FT245R USB FIFO IC The FT245R is a USB to parallel FIFO interface with the following advanced features: • Single chip USB to parallel FIFO bidirectional
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FT245R
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XR16C8641
Abstract: EXAR MARKING CODE intel date code marking qfp100
Text: XR16C864 -Quad UART with RX/TX FIFO Counters and 128-Byte FIFO HomeNewsCareers Investor Relations Contact Us PartnerNet Login Search CommunicationsInterfacePower Management XR16C864 Support Info Request How to Order Samples How to Buy Print this page Quad UART with RX/TX FIFO Counters and 128-Byte FIFO
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XR16C864
128-Byte
ST16C554/654,
ST68C554/654,
XR16C8641
EXAR MARKING CODE
intel date code marking qfp100
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XC4VLX15-FF668
Abstract: axi4 XC4VLX15-FF668-10 FIFO Generator User Guide XQR XQ artix7 ucf file XC6SLX150T-FGG484-2 LocalLink axi wrapper XILINX/fifo generator xilinx spartan
Text: LogiCORE IP FIFO Generator v8.3 DS317 October 19, 2011 Product Specification Introduction The Xilinx LogiCORE IP FIFO Generator is a fully verified first-in first-out FIFO memory queue for applications requiring in-order storage and retrieval. The core provides an optimized solution for all FIFO
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DS317
XC4VLX15-FF668
axi4
XC4VLX15-FF668-10
FIFO Generator User Guide
XQR XQ
artix7 ucf file
XC6SLX150T-FGG484-2
LocalLink
axi wrapper
XILINX/fifo generator xilinx spartan
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XC7V2000TFLG1925
Abstract: XC7V2000T-FLG1925-1 XC7K480T-FFG1156-1 XC6SLX150T-FGG900 Artix-7 FFG1156 xc5vlx XC6VLX760-FF1760-1 XILINX/fifo generator xilinx spartan
Text: LogiCORE IP FIFO Generator v9.1 DS317 April 24, 2012 Product Specification Introduction The Xilinx LogiCORE IP FIFO Generator is a fully verified first-in first-out FIFO memory queue for applications requiring in-order storage and retrieval. The core provides an optimized solution for all FIFO
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DS317
XC7V2000TFLG1925
XC7V2000T-FLG1925-1
XC7K480T-FFG1156-1
XC6SLX150T-FGG900
Artix-7
FFG1156
xc5vlx
XC6VLX760-FF1760-1
XILINX/fifo generator xilinx spartan
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XILINX ft2232
Abstract: usb eeprom programmer schematic 1 MEGA OHM RESISTOR FT2232C 2430 opto coupler canbus converter rohs FT245 FTDI FT245 USB FIFO device data sheet tri-color led xilinx datasheet fifo generator 6.2
Text: FT2232C Dual USB UART / FIFO I.C. 1.0 Introduction The FT2232C is the 3rd generation of FTDI’s popular USB UART / FIFO I.C. family. This device features two MultiPurpose UART / FIFO controllers which can be configured individually in several different modes. As well as a UART
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FT2232C
FT232BM
FT245BM
FT2232C
DS2232C
XILINX ft2232
usb eeprom programmer schematic
1 MEGA OHM RESISTOR
2430 opto coupler
canbus converter rohs
FT245
FTDI FT245 USB FIFO device data sheet
tri-color led
xilinx datasheet fifo generator 6.2
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IN SDLC PROTOCOL
Abstract: WR10 Z85230 Z85233 nrzi encoding
Text: ENHANCED M ONO SCC ZILOG PRODUCT BRIEF Z85233 EMSCC ENHANCED MONO SERIAL COMMUNICATION CONTROLLER FEATURES • Hardware and software compatible with Zilog's SCC/ ESCC™ ■ Deeper Data FIFOs - 4-Byte Transmit FIFO - 8-Byte Receive FIFO ■ Improved SDLC Frame Status FIFO
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Z85233
Z85233
IN SDLC PROTOCOL
WR10
Z85230
nrzi encoding
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IN SDLC PROTOCOL
Abstract: WR10 Z85230 Z85233
Text: ENHANCED M ONO SCC ZILOG PRODUCT BRIEF Z85233 EMSCC ENHANCED MONO SERIAL COMMUNICATION CONTROLLER FEATURES • Hardware and software compatible with Zilog's SCC/ ESCC™ ■ Deeper Data FIFOs - 4-Byte Transmit FIFO - 8-Byte Receive FIFO ■ Improved SDLC Frame Status FIFO
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Z85233
Z85233
PB005801-0201
IN SDLC PROTOCOL
WR10
Z85230
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Untitled
Abstract: No abstract text available
Text: FT2232C Dual USB UART / FIFO I.C. 1.0 Introduction The FT2232C is the 3rd generation of FTDI’s popular USB UART / FIFO I.C. family. This device features two MultiPurpose UART / FIFO controllers which can be configured individually in several different modes. As well as a UART
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FT2232C
FT232BM
FT245BM
FT2232C
DS2232C
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Untitled
Abstract: No abstract text available
Text: CY7C421512 x 9 Asynchronous FIFO CY7C421 512 × 9 Asynchronous FIFO 512 × 9 Asynchronous FIFO Features • Asynchronous First-In First-Out FIFO Buffer Memories ❐ 512 × 9 (CY7C421) ■ Dual-Ported RAM Cell ■ High Speed 50 MHz Read and Write Independent of Depth and
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CY7C421512
CY7C421
CY7C421)
300-Mil
IDT7201,
AM7201
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Untitled
Abstract: No abstract text available
Text: CY7C421512 x 9 Asynchronous FIFO CY7C421 512 × 9 Asynchronous FIFO 512 × 9 Asynchronous FIFO Features • Asynchronous First-In First-Out FIFO Buffer Memories ❐ 512 × 9 (CY7C421) ■ Dual-Ported RAM Cell ■ High Speed 50 MHz Read and Write Independent of Depth and
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CY7C421512
CY7C421
CY7C421)
300-Mil
IDT7201,
AM7201
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LH5481
Abstract: LH5491
Text: LH5481 LH5491 FEATURES • Fastest 64 x 8/9 Cascadable FIFO 35/25/15 MHz • Expandable in Word Width and FIFO Depth • Almost-Full/Almost-Empty and Half-Full Flags • Fully Independent Asynchronous Inputs and Outputs Cascadable 64 × 8 FIFO Cascadable 64 × 9 FIFO
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LH5481
LH5491
28-PIN
LH5481
28PLCC
28-pin,
450-mil
LH5481/91
300-mil
LH5491
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greatek
Abstract: USB FT240x FT240X FT240XQ FT232R timing diagram
Text: FT240X USB 8-BIT FIFO IC Datasheet Version 1.0 Document No.: FT_000626 Clearance No.: FTDI# 259 Future Technology Devices International Ltd. FT240X USB 8-BIT FIFO IC The FT240X is a USB to parallel FIFO interface with the following advanced features: Single chip USB to parallel FIFO bidirectional
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FT240X
FT240X
greatek
USB FT240x
FT240XQ
FT232R timing diagram
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cym4241pd
Abstract: CYM4241
Text: PRELIMINARY CYPRESS SEMICONDUCTOR 64K x 9 FIFO Features Functional Description • 65,536 x 9 FIFO buffer memory The CYM4241 RAM FIFO is a 65.536-word by 9-bit first-in first-out FIFO memory implemented using an ad vanced SRAM controller architecture.
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28-pin,
600-m
7C428,
7C432)
CYM4241
536-word
600-mil
CYM4241PD-85C
cym4241pd
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Untitled
Abstract: No abstract text available
Text: LH54817 LH5491 FEATURES • • Fastest 64 x 8/9 Cascadeable FIFO 35/25/15 MHz Expandable in Word Width & FIFO Depth Cascadeable 64 x 8 FIFO Cascadeable 64 x 9 FIFO high speed makes these FIFOs ideal for high perfor mance communication and controller applications.
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LH54817
LH5491
LH5481
LH5485/5495
28-Pin,
300-mil
28-Pin
LH5481/91
28-Din.
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dln 2003
Abstract: ScansU9X24 64x8
Text: LH5481 LH5491 Cascadable 64 x 8 FIFO Cascadable 64 x 9 FIFO FEATURES • Fastest 64 x 8/9 Cascadable FIFO 35/25/15 MHz • Expandable in Word Width and FIFO Depth • Almost-Full/Almost-Empty and Half-Full Flags Half-Full HF flag is asserted (HIGH) when the FIFO
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LH5481
LH5491
64x8/9
CY7C408A/09A
L8C408/09
28-Pin,
300-mil
28-Pin
TheLH5481
dln 2003
ScansU9X24
64x8
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lh5495
Abstract: No abstract text available
Text: LH5485 / LH5495 FEATURES • Fastest 256 x 8/9 Cascadeable FIFO 35/25/15 MHz • Expandable in Word Width & FIFO Depth • Almost-Full / Empty & Half-Full Flags • Fully Independent Asynchronous Inputs & Outputs • Cascadeable 256 x 8 FIFO Cascadeable 256 x 9 FIFO
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LH5485
LH5495
LH5481/5491
28-Pin,
300-mil
28-Pin
5485-ID
LH5485/95
lh5495
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256x
Abstract: No abstract text available
Text: LH5485 LH5495 FEATURES • Fastest 256 x 8/9 Cascadeable FIFO 35/25/15 MHz • Expandable in Word Width & FIFO Depth • Almost-Full / Empty & Half-Full Flags • Fully Independent Asynchronous Inputs & Outputs • Cascadeable 256 x 8 FIFO Cascadeable 256 x 9 FIFO
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LH5485
LH5495
LH5481/5491
28-Pin,
300-mil
28-Pin
256x
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ISP9119
Abstract: No abstract text available
Text: o o > • ' . 'H y ISP9119 GE Solid State FIFO RAM Controller GENERAL DESCRIPTION FEATURES The ISP9119 FIFO RAM Controller FRC , together with a static RAM array, forms a First-In-First-Out (FIFO) buffer. The ISP9119 FRC, implemented in Intersil’s 1.5 micron
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ISP9119
FIFOs-16
ISP9119
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