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Catalog Datasheet	MFG & Type	PDF	Document Tags
EPM7256 PIN Abstract: No abstract text available Text: ALTERA bflE CORP D • DS1S372 GGD3272 T7S « A L T EPM7256 EPLD Features □ □ □ □ □ □ High-density, erasable CMOS EPLD based on second-generation MAX architecture 5,000 usable gates Combinatorial speeds with tPD = 20 ns Higher speed versions under development	OCR Scan	PDF	DS1S372 GGD3272 EPM7256 192-pin 208-pin EPM7256 PIN
EPM7256 Abstract: fp 221 25.b EPM7256-25 EPM7256 PIN EPM7256-20 DDD3271 B1395 HA1084 NN37 KE236 Text: ALTERA bflE D CORP • DS1S372 GGD3272 T7S « A L T EPM7256 EPLD Features □ □ □ □ □ □ High-density, erasable CMOS EPLD based on second-generation MAX architecture 5,000 usable gates Combinatorial speeds with tPD = 20 ns Higher speed versions under development	OCR Scan	PDF	DS1S372 192-pin 208-pin EPM7256 fp 221 25.b EPM7256-25 EPM7256 PIN EPM7256-20 DDD3271 B1395 HA1084 NN37 KE236
Altera EP1810 Abstract: No abstract text available Text: ALTERA CORP 47E D • 05*15372 DQ0211b 376 ■ ALT T ^ to -o / EP1810 EPLD s A N b [m □ □ □ □ □ □ □ □ □ □ High-density replacement for TTL and 74HC High-performance 48-macrocell EPLD with tPD = 20 ns and counter frequencies up to 50 MHz	OCR Scan	PDF	000211b EP1810 48-Macrocell EP1830-20, EP1830-25, EP1830-30 EP1830-25 EP1830 Altera EP1810
Altera EPM5128 Abstract: WKX 62 EPM5016 epm5130 pinouts for 7400 series EPM5064 EPM5192 program EPM5032 EPM5128 PACKAGING PLDS-MAX Text: EPM5016 to EPM5192 EPLDs High-Speed, High-Density MAX 5000 Devices Data Sheet September 1991, ver. 2 Features □ □ □ □ □ □ Complete family of CMOS EPLDs solves design tasks ranging from fast 20-pin address decoders to 100-pin LSI custom peripherals.	OCR Scan	PDF	EPM5016 EPM5192 20-pin 100-pin 15-ns Altera EPM5128 WKX 62 epm5130 pinouts for 7400 series EPM5064 program EPM5032 EPM5128 PACKAGING PLDS-MAX
55B0 Abstract: Signal Path designer Text: FLEX 6000 Programmable Logic Device Family June 1997, ver. 2 Data Sheet Introduction W ith a prim ary focus on low cost, the Altera FLEX® 6000 device family provides an ideal program m able alternative to high-volume gate-array applications. Because FLEX 6000 devices are programmable, fast design	OCR Scan	PDF	EPF6010QC208 G557c 55B0 Signal Path designer
r12n10 Abstract: EMP7032 max7000 Text: Includes MAX7000E M A Y IVI M A 7 0 0 0 / UUU Programmable Logic Device Family March 1995, ver. 3 Features. Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance CMOS EEPROM devices based on secondgeneration Multiple Array MatriX MAX architecture	OCR Scan	PDF	MAX7000E EPM7256E 192-Pin 208-Pin r12n10 EMP7032 max7000
EPX880-10 Abstract: altera epx740 Text: FLASHIogic Programmable Logic Device Family Features. • ■ Prelim inary Information ■ ■ ■ Formerly Intel's FLEXlogic iFX family High-performance programmable logic device (PLD) family SRAM-based logic w ith shadow EPROM or FLASH memory elements fabricated on 0.6- and 0.8-micron CMOS technology	OCR Scan	PDF	24V10 EPX880 84-Pin 160-Pin EPX8160 EPX8160 DS1S372 208-Pin EPX880-10 altera epx740
EP1830 Abstract: EP1810 jedec 74HC EP1810 EP18302 EP1830 jedec Text: EP1810 EPLDs High-Performance 48-Macrocell Devices Data Sheet September 1991, ver. 2 Features □ □ □ □ □ □ □ Q General Description The EP1810 Erasable Programmable Logic Devices EPLDs offer LSI density,TTL-equivalentspeed, and low power consumption. Each EPLD can	OCR Scan	PDF	EP1810 48-Macrocell EP1830-20, EP1830-25, EP1830-30 EP1830-25 EP1830 EP1810 jedec 74HC EP18302 EP1830 jedec
EP610 Abstract: Altera September 1991 EP610-20 acht30 Text: altera M7E D corp 05^5375 ODDgPbb T lg W ALT EP610 EPLDs High-Performance 16-Macrocell Devices Data Sheet September 1991, ver. 2 □ □ Features □ □ □ □ □ □ □ □ □ General Description H igh-density replacem ent for TTL and 74HC w ith up to 600 gates	OCR Scan	PDF	EP610 16-Macrocell EP630-20 EP630-15, EP630-20 EP630 Altera September 1991 EP610-20 acht30