Untitled
Abstract: No abstract text available
Text: DATA SHEET MOS INTEGRATED CIRCUIT PD48288118 288M-BIT Low Latency DRAM Separate I/O Description The μPD48288118 is a 16,777,216 word by 18 bit synchronous double data rate Low Latency RAM fabricated with advanced CMOS technology using one-transistor memory cell.
|
Original
|
PDF
|
PD48288118
288M-BIT
PD48288118
|
p144f
Abstract: TDK EF25 BAP36 PD482
Text: DATA SHEET MOS INTEGRATED CIRCUIT PD48288118-A 288M-BIT Low Latency DRAM Separate I/O Description The μPD48288118-A is a 16,777,216 word by 18 bit synchronous double data rate Low Latency RAM fabricated with advanced CMOS technology using one-transistor memory cell.
|
Original
|
PDF
|
PD48288118-A
288M-BIT
PD48288118-A
M8E0904E
p144f
TDK EF25
BAP36
PD482
|
Untitled
Abstract: No abstract text available
Text: Datasheet PD48288118-A 288M-BIT Low Latency DRAM Separate I/O R10DS0157EJ0100 Rev.1.00 Feb 01, 2013 Description The μPD48288118-A is a 16,777,216 word by 18 bit synchronous double data rate Low Latency RAM fabricated with advanced CMOS technology using one-transistor memory cell.
|
Original
|
PDF
|
PD48288118-A
288M-BIT
R10DS0157EJ0100
PD48288118-A
|
Untitled
Abstract: No abstract text available
Text: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT PD48288118 288M-BIT Low Latency DRAM Separate I/O Description The μPD48288118 is a 16,777,216 word by 18 bit synchronous double data rate Low Latency RAM fabricated with advanced CMOS technology using one-transistor memory cell.
|
Original
|
PDF
|
PD48288118
288M-BIT
PD48288118
|
BA2rc
Abstract: No abstract text available
Text: DATA SHEET MOS INTEGRATED CIRCUIT PD48288118 288M-BIT Low Latency DRAM Separate I/O Description The μPD48288118 is a 16,777,216 word by 18 bit synchronous double data rate Low Latency RAM fabricated with advanced CMOS technology using one-transistor memory cell.
|
Original
|
PDF
|
PD48288118
288M-BIT
PD48288118
BA2rc
|
PD48576109,
Abstract: No abstract text available
Text: Datasheet PD48576109 μPD48576118 R10DS0064EJ0100 Rev.1.00 September 27, 2011 576M-BIT Low Latency DRAM Separate I/O Description The μPD48576109 is a 67,108,864-word by 9 bit and the μPD48576118 is a 33,554,432 word by 18 bit synchronous double data rate Low Latency RAM fabricated with advanced CMOS technology using one-transistor memory cell.
|
Original
|
PDF
|
PD48576109
PD48576118
576M-BIT
864-word
PD48576118
R10DS0064EJ0100
PD48576109,
|
Untitled
Abstract: No abstract text available
Text: Datasheet PD48288109A μPD48288118A R10DS0098EJ0200 Rev.2.00 May 10, 2012 288M-BIT Low Latency DRAM Separate I/O Description The μPD48288109A is a 33,554,432-word by 9 bit and the μPD48288118A is a 16,777,216-word by 18 bit synchronous double data rate Low Latency RAM fabricated with advanced CMOS technology using one-transistor memory cell.
|
Original
|
PDF
|
PD48288109A
PD48288118A
288M-BIT
432-word
PD48288118A
216-word
R10DS0098EJ0200
|
Untitled
Abstract: No abstract text available
Text: Datasheet PD48288109A μPD48288118A R10DS0098EJ0300 Rev.3.00 Oct 01, 2012 288M-BIT Low Latency DRAM Separate I/O Description The μPD48288109A is a 33,554,432-word by 9 bit and the μPD48288118A is a 16,777,216-word by 18 bit synchronous double data rate Low Latency RAM fabricated with advanced CMOS technology using one-transistor memory cell.
|
Original
|
PDF
|
PD48288109A
PD48288118A
288M-BIT
432-word
PD48288118A
216-word
R10DS0098EJ0300
|
Untitled
Abstract: No abstract text available
Text: Datasheet PD48576109 μPD48576118 R10DS0064EJ0300 Rev.3.00 Oct 01, 2012 576M-BIT Low Latency DRAM Separate I/O Description The μPD48576109 is a 67,108,864-word by 9 bit and the μPD48576118 is a 33,554,432 word by 18 bit synchronous double data rate Low Latency RAM fabricated with advanced CMOS technology using one-transistor memory cell.
|
Original
|
PDF
|
PD48576109
PD48576118
576M-BIT
864-word
PD48576118
R10DS0064EJ0300
|
Untitled
Abstract: No abstract text available
Text: Datasheet PD48576109 μPD48576118 R10DS0064EJ0200 Rev.2.00 May 10, 2012 576M-BIT Low Latency DRAM Separate I/O Description The μPD48576109 is a 67,108,864-word by 9 bit and the μPD48576118 is a 33,554,432 word by 18 bit synchronous double data rate Low Latency RAM fabricated with advanced CMOS technology using one-transistor memory cell.
|
Original
|
PDF
|
PD48576109
PD48576118
576M-BIT
864-word
PD48576118
R10DS0064EJ0200
|
Untitled
Abstract: No abstract text available
Text: Preliminary Datasheet PD48288109A μPD48288118A R10DS0098EJ0001 Rev.0.01 August 2, 2011 288M-BIT Low Latency DRAM Separate I/O Description The μPD48288109A is a 33,554,432-word by 9 bit and the μPD48288118A is a 16,777,216-word by 18 bit synchronous double data rate Low Latency RAM fabricated with advanced CMOS technology using one-transistor memory cell.
|
Original
|
PDF
|
PD48288109A
PD48288118A
R10DS0098EJ0001
288M-BIT
PD48288109A
432-word
PD48288118A
216-word
|
Untitled
Abstract: No abstract text available
Text: Datasheet PD48288109A μPD48288118A R10DS0098EJ0100 Rev.1.00 February 28, 2012 288M-BIT Low Latency DRAM Separate I/O Description The μPD48288109A is a 33,554,432-word by 9 bit and the μPD48288118A is a 16,777,216-word by 18 bit synchronous double data rate Low Latency RAM fabricated with advanced CMOS technology using one-transistor memory cell.
|
Original
|
PDF
|
PD48288109A
PD48288118A
288M-BIT
432-word
PD48288118A
216-word
R10DS0098EJ0100
|
BA1 K11
Abstract: ba1d1a PD48576118FF-E24-DW1-A
Text: Preliminary Datasheet PD48576109-A μPD48576118-A R10DS0064EJ0001 Rev.0.01 Nov 08, 2010 576M- Low Latency DRAM Separate I/O Description The μPD48576109-A is a 67,108,864-word by 9 bit and the μPD48576118-A is a 33,554,432 word by 18 bit synchronous double data rate Low Latency RAM fabricated with advanced CMOS technology using one-transistor memory cell.
|
Original
|
PDF
|
PD48576109-A
PD48576118-A
R10DS0064EJ0001
PD48576109-A
864-word
PD48576118-A
BA1 K11
ba1d1a
PD48576118FF-E24-DW1-A
|
SWITCH 255SB
Abstract: MA05-2 pin header nanoLOC TRX Transceiver user guide nanoLOC nanoLOC Development d-sub F09HP all stk ic diagram crystal 7.3728MHz zigbee based mini projects tsl2561t
Text: nanoLOC Development Kit User Guide Version 1.03 NA-06-0230-0402-1.03 Document Information nanoLOC Development Kit User Guide Document Information Document Title: nanoLOC Development Kit User Guide Document Version: 1.03 Published yyyy-mm-dd : 2007-02-27 Current Printing:
|
Original
|
PDF
|
NA-06-0230-0402-1
SWITCH 255SB
MA05-2 pin header
nanoLOC TRX Transceiver user guide
nanoLOC
nanoLOC Development
d-sub F09HP
all stk ic diagram
crystal 7.3728MHz
zigbee based mini projects
tsl2561t
|
|
LLDRAM
Abstract: No abstract text available
Text: Preliminary GS4576C09/18/36L 144-Ball BGA Commercial Temp Industrial Temp 64M x 9, 32M x 18, 16M x 36 576Mb CIO Low Latency DRAM LLDRAM II 533 MHz–300 MHz 2.5 V VEXT 1.8 V VDD 1.5 V or 1.8 V VDDQ Features Introduction • Pin- and function-compatible with Micron RLDRAM II
|
Original
|
PDF
|
GS4576C09/18/36L
144-Ball
067Gb/s/pin
4576Cxx
LLDRAM
|
LM8327
Abstract: No abstract text available
Text: LM8327 Mobile I/O Companion Supporting Keyscan, I/O Expansion, PWM, and ACCESS.bus Host Interface 1.0 General Description The LM8327 GenI/O-Expander and Keypad Controller is a dedicated device to unburden a host processor from scanning a matrix-addressed keypad and to provide flexible and general purpose, host-programmable input/output functions.
|
Original
|
PDF
|
LM8327
|
Untitled
Abstract: No abstract text available
Text: Preliminary GS4288S09/18L 144-Ball BGA Commercial Temp Industrial Temp 32M x 9, 16M x 18 288Mb SIO Low Latency DRAM LLDRAM II 533 MHz–300 MHz 2.5 V VEXT 1.8 V VDD 1.5 V or 1.8 V VDDQ Features Introduction • Pin- and function-compatible with Micron RLDRAM II
|
Original
|
PDF
|
GS4288S09/18L
144-Ball
067Gb/s/pin
outpu44-ball
GS4288S09-533T.
288Mb
4288Sxx
|
A211
Abstract: A212 A221
Text: Preliminary GS4576S09/18L 144-Ball BGA Commercial Temp Industrial Temp 64M x 9, 32M x 18 576Mb SIO Low Latency DRAM LLDRAM II 533 MHz–300 MHz 2.5 V VEXT 1.8 V VDD 1.5 V or 1.8 V VDDQ Features Introduction • Pin- and function-compatible with Micron RLDRAM II
|
Original
|
PDF
|
GS4576S09/18L
144-Ball
576Mb
067Gb/s/pin
GS4576S09-533T.
4576Sxx
A211
A212
A221
|
LLDRAM
Abstract: 144BallBGA A212 A221 ba2163 J2/GS4576C09GL-24I
Text: Preliminary GS4576C09/18/36L 144-Ball BGA Commercial Temp Industrial Temp 64M x 9, 32M x 18, 16M x 36 576Mb CIO Low Latency DRAM LLDRAM II 533 MHz–300 MHz 2.5 V VEXT 1.8 V VDD 1.5 V or 1.8 V VDDQ Features Introduction • Pin- and function-compatible with Micron RLDRAM II
|
Original
|
PDF
|
GS4576C09/18/36L
144-Ball
576Mb
067Gb/s/pin
4576Cxx
LLDRAM
144BallBGA
A212
A221
ba2163
J2/GS4576C09GL-24I
|
J2/GS4576C09GL-24I
Abstract: No abstract text available
Text: Preliminary GS4576C09/18/36L 144-Ball BGA Commercial Temp Industrial Temp 64M x 9, 32M x 18, 16M x 36 576Mb CIO Low Latency DRAM LLDRAM II 533 MHz–300 MHz 2.5 V VEXT 1.8 V VDD 1.5 V or 1.8 V VDDQ Features Introduction • Pin- and function-compatible with Micron RLDRAM II
|
Original
|
PDF
|
GS4576C09/18/36L
144-Ball
067Gb/s/pin
4576Cxx
J2/GS4576C09GL-24I
|
Untitled
Abstract: No abstract text available
Text: Preliminary GS4576S09/18L 144-Ball BGA Commercial Temp Industrial Temp 64M x 9, 32M x 18 576Mb SIO Low Latency DRAM LLDRAM II 533 MHz–300 MHz 2.5 V VEXT 1.8 V VDD 1.5 V or 1.8 V VDDQ Features Introduction • Pin- and function-compatible with Micron RLDRAM II
|
Original
|
PDF
|
GS4576S09/18L
144-Ball
067Gb/s/pin
GS4576S09-533T.
576Mb
4576Sxx
|
DK97
Abstract: RLDRAM J2/GS4576C09GL-24I
Text: Preliminary GS4576C09/18/36L 144-Ball BGA Commercial Temp Industrial Temp 64M x 9, 32M x 18, 16M x 36 576Mb CIO Low Latency DRAM LLDRAMTM II 533 MHz–300 MHz 2.5 V VEXT 1.8 V VDD 1.5 V or 1.8 V VDDQ Features Introduction • Pin- and function-compatible with Micron RLDRAM II
|
Original
|
PDF
|
GS4576C09/18/36L
144-Ball
067Gb/s/pin
576Mb
4576Cxx
DK97
RLDRAM
J2/GS4576C09GL-24I
|
DK97
Abstract: J2/GS4576C09GL-24I
Text: Preliminary GS4576C09/18/36L 144-Ball BGA Commercial Temp Industrial Temp 64M x 9, 32M x 18, 16M x 36 576Mb CIO Low Latency DRAM LLDRAMTM II 533 MHz–300 MHz 2.5 V VEXT 1.8 V VDD 1.5 V or 1.8 V VDDQ Features Introduction • Pin- and function-compatible with Micron RLDRAM II
|
Original
|
PDF
|
GS4576C09/18/36L
144-Ball
067Gb/s/pin
576Mb
4576Cxx
DK97
J2/GS4576C09GL-24I
|
J2/GS4576C09GL-24I
Abstract: No abstract text available
Text: Preliminary GS4576C09/18/36L 144-Ball BGA Commercial Temp Industrial Temp 64M x 9, 32M x 18, 16M x 36 576Mb CIO Low Latency DRAM LLDRAM II 533 MHz–300 MHz 2.5 V VEXT 1.8 V VDD 1.5 V or 1.8 V VDDQ Features Introduction • Pin- and function-compatible with Micron RLDRAM II
|
Original
|
PDF
|
GS4576C09/18/36L
144-Ball
067Gb/s/pin
576Mb
4576Cxx
J2/GS4576C09GL-24I
|