7B SMD
Abstract: No abstract text available
Text: Surface Mount SMD Packaging Reel and Carrier Tape Specifications MINIMUM PACKING QUANTITY DFN Series (Notes 4) DFN0806 DFN0808 Bulk Type Quantity NA NA NA DFN1006 NA DFN1010 NA DFN1409, DFN1410 DFN/QFN3030 (Note 5) DFN4030-12 DFN4030-12 Type B, C, D NA NA
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DFN0806
DFN0808
DFN1006
DFN1010
DFN1409,
DFN1410
DFN/QFN3030
DFN4030-12
DFN4030-12
QFN4040
7B SMD
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Untitled
Abstract: No abstract text available
Text: 74AUP1G126 SINGLE BUFFER GATE WITH 3-STATE OUTPUT Description Pin Assignments The Advanced Ultra Low Power AUP CMOS logic family is designed (Top View) for low power and extended battery life in portable applications. The 74AUP1G126 is a single non-inverting buffer/bus driver designed
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74AUP1G126
74AUP1G126
OT353
DS35158
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74AUP1G86SE
Abstract: No abstract text available
Text: 74AUP1G86 SINGLE 2 INPUT EXCLUSIVE-OR GATE Description Pin Assignments The Advanced Ultra Low Power AUP CMOS logic family is designed for low power and extended battery life in portable applications. The 74AUP1G86 is a single 2-input positive exclusive-OR gate with a
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74AUP1G86
74AUP1G86
DS35156
74AUP1G86SE
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74AUP1G07SE-7
Abstract: 74AUP1G07
Text: 74AUP1G07 SINGLE BUFFER/DRIVER WITH OPEN DRAIN OUTPUT Description Pin Assignments The Advanced Ultra Low Power AUP CMOS logic family is designed for low power and extended battery life in portable applications. The 74AUP1G07 is a single buffer gate with an open drain output
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74AUP1G07
74AUP1G07
DS35149
74AUP1G07SE-7
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NX3008NBKMB
Abstract: IP4303CX4 PCMF2DFN1
Text: Safeguard sensitive ICs - Increase battery life - Save space With NXP key products as recommended in this brochure Interface / Function Description Product type Package NFC antenna protection 18 / 24 V Birectional low capacitance ESD protection diode PESD18VF1BL
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PESD18VF1BL
PESD24VF1BL
PESD18VF1BSF
PESD24VF1BSF
DFN1006
DSN0603
DFN2520
DFN4020
NX3008NBKMB
IP4303CX4
PCMF2DFN1
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Untitled
Abstract: No abstract text available
Text: High PSRR LDOs Dual Channel LDOs with High PSRR Performance Package DFN1612-8 SOT1225 LD6935 Series Size (mm) 1.6 x 1.2 x 0.4 mm Ptot @ °C (mW) VIN (V) 600 Quiescent Output PSRR @ current noise typ 1 kHz (µA) * (µVrms) (dB) 1.75 5.5 30 50 80 IOUT (mA)
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DFN1612-8
OT1225)
LD6935
LD6935L/xxH
LD6935L/xxP
LD6935L/xxHD
LD6935L/xxPD
LD6935L/2826H
LD6935L/2826P
LD6935L/2828H
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SCHMITT-TRIGGER
Abstract: 74lvc1g17se-7 74LVC1G17
Text: 74LVC1G17 SINGLE SCHMITT-TRIGGER BUFFER Description Pin Assignments Top View The 74LVC1G17 is a single 1-input Schmitt-trigger buffer with NC 1 a standard totem pole output. The device is designed for operation with a power supply range of 1.65V to 5.5V. The
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74LVC1G17
74LVC1G17
OT353
DS35124
SCHMITT-TRIGGER
74lvc1g17se-7
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Untitled
Abstract: No abstract text available
Text: 74LVC1G97 CONFIGURABLE MULTIPLE-FUNCTION GATE Description Pin Assignments Top View The 74LVC1G97 is a single 3-input positive configurable multiple function gate with a standard push-pull output. The output state is determined by eight patterns of 3-bit input.
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74LVC1G97
74LVC1G97
OT363
DS35127
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Untitled
Abstract: No abstract text available
Text: 74LVC1G02 SINGLE 2 INPUT POSITIVE NOR GATE Description Pin Assignments Top View ( Top View ) The 74LVC1G02 is a single 2-input positive NOR gate with a standard push-pull output. The device is designed for operation with A 1 5 Vcc A 1 5 Vcc B 2 a power supply range of 1.65V to 5.5V. The inputs are tolerant to
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74LVC1G02
74LVC1G02
OT553
OT353
DS32197
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Untitled
Abstract: No abstract text available
Text: 74AUP1G14 SINGLE SCHMITT-TRIGGER INVERETER Description Pin Assignments The Advanced Ultra Low Power AUP CMOS logic family is ( Top View ) designed for low power and extended battery life in portable ( Top View ) applications. NC 1 5 Vcc The AUP1G14 is a single 1-input Schmitt-trigger inverter gate with
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74AUP1G14
AUP1G14
X2-DFN0808-4
OT353
DS35152
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Untitled
Abstract: No abstract text available
Text: 74AUP1G17 SINGLE SCHMITT-TRIGGER BUFFER Description Pin Assignments The Advanced Ultra Low Power AUP CMOS logic family is designed ( Top View ) for low power and extended battery life in portable applications. ( Top View ) NC 1 The AUP1G17 is a single 1-input Schmitt-trigger buffer gate with a
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74AUP1G17
AUP1G17
X2-DFN0808-4
OT353
DS35153
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Untitled
Abstract: No abstract text available
Text: 74AUP2G17 DUAL SCHMITT TRIGGER BUFFERS Description Pin Assignments The Advanced Ultra Low Power AUP CMOS logic family is designed for low power and extended battery life in portable applications. The 74AUP2G17 is composed of two Schmitt trigger buffers with
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74AUP2G17
74AUP2G17
DS35513
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Untitled
Abstract: No abstract text available
Text: 74LVC1G08 SINGLE 2 INPUT POSITIVE AND GATE Description Pin Assignments The 74LVC1G08 is a single 2-input positive AND gate with a standard push-pull output. The device is designed for operation with a power supply range of 1.65V to 5.5V. The inputs are tolerant to 5.5V allowing
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74LVC1G08
74LVC1G08
DS32199
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Untitled
Abstract: No abstract text available
Text: 74AUP1G09 SINGLE 2 INPUT POSITIVE AND GATE WITH OPEN DRAIN OUTPUT Description Pin Assignments The Advanced Ultra Low Power AUP CMOS logic family is designed for low power and extended battery life in portable ( Top View ) applications. ( Top View ) 5 Vcc
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74AUP1G09
AUP1G09
X2-DFN0808-4
OT35nowledge
DS35151
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circuit diagram wireless spy camera
Abstract: PDTB123Y IP4303CX4 dual cc BAW62 3267 tsop6 PCMF2DFN1 BST60 PUMD4 PDTB123E PDTA143
Text: Discrete Semiconductors Selection Guide 2014 Protection and signal conditioning devices, diodes, bipolar transistors, MOSFETs and thyristors. NXP’s next generation of packaging DFN Discrete Flat No-lead packages – high performance on smallest footprint
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DFN1006D-2
OD882D)
DFN1010D-3
OT1215)
DFN2020MD-6
OT1220)
DFN1608D-2
OD1608)
DSN0603
OD962)
circuit diagram wireless spy camera
PDTB123Y
IP4303CX4
dual cc BAW62
3267 tsop6
PCMF2DFN1
BST60
PUMD4
PDTB123E
PDTA143
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Untitled
Abstract: No abstract text available
Text: 74LVCE1G126 SINGLE BUFFER GATE WITH 3-STATE OUTPUT Description Pin Assignments Top View The 74LVCE1G126 is a single non-inverting buffer/bus driver with a 3-state output. The output enters a high impedance state when a LOW-level is applied to the output enable (OE)
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74LVCE1G126
74LVCE1G126
OT353
DS32217
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AA112A
Abstract: IPC-7351A
Text: PACKAGE OUTLINE DIMENSIONS AP02002 SUGGESTED PAD LAYOUT(AP02001) (Based on IPC-7351A) Table of Contents X4-DFN0402‐2/SWP . 10
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AP02002)
AP02001)
IPC-7351A)
DFN0402â
DFN0603â
DFN0606â
IPC-7351A,
AA112A
IPC-7351A
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JESD30E
Abstract: 74AUP1G00
Text: 74AUP1G00 SINGLE 2 INPUT POSITIVE NAND GATE Description Pin Assignments The Advanced Ultra Low Power AUP CMOS logic family is designed for low power and extended battery life in portable applications. The 74AUP1G00 is a single 2-input positive NAND gate with a
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74AUP1G00
74AUP1G00
DS35145
JESD30E
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Marking code VM sot35
Abstract: VM MARKING CODE SOT353
Text: 74LVC1G07 SINGLE BUFFER/DRIVER WITH OPEN DRAIN OUTPUT Description Pin Assignments The 74LVC1G07 is a single inverter gate with an open drain Top View output. The device is designed for operation with a power supply range of 1.65V to 5.5V. The input is tolerant to 5.5V
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74LVC1G07
74LVC1G07
OT353
DS32274
Marking code VM sot35
VM MARKING CODE SOT353
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Untitled
Abstract: No abstract text available
Text: 74LVC1G32 SINGLE 2 INPUT POSITIVE OR GATE Description Pin Assignments The 74LVC1G32 is a single 2-input positive OR gate with a Top View standard push-pull output. The device is designed for operation with a power supply range of 1.65V to 5.5V. The A 1 5
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74LVC1G32
74LVC1G32
OT353
DS32200
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Untitled
Abstract: No abstract text available
Text: 74LVC1G98 CONFIGURABLE MULTIPLE-FUNCTION GATE Description Pin Assignments Top View The 74LVC1G98 is a single 3-input positive configurable multiple function gate with a standard push-pull output. The output state is determined by eight patterns of 3-bit input.
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74LVC1G98
74LVC1G98
OT363
DS35128
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sot35
Abstract: No abstract text available
Text: 74LVC1G06 SINGLE INVERTER BUFFER/DRIVER WITH OPEN DRAIN OUTPUT Description Pin Assignments Top View The 74LVC1G06 is a single inverter gate with an open drain output. The device is designed for operation with a power NC 1 supply range of 1.65V to 5.5V. The input is tolerant to 5.5V
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74LVC1G06
74LVC1G06
OT353
DS32272
sot35
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74LVC1G02W57
Abstract: No abstract text available
Text: 74LVC1G02 SINGLE 2 INPUT POSITIVE NOR GATE Description Pin Assignments Top View (Top View) The 74LVC1G02 is a single 2-input positive NOR gate with a standard push-pull output. The device is designed for A 1 operation with a power supply range of 1.65V to 5.5V. The
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74LVC1G02
74LVC1G02
OT353
DS32197
74LVC1G02W57
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Untitled
Abstract: No abstract text available
Text: 74LVC1G97 CONFIGURABLE MULTIPLE-FUNCTION GATE Description Pin Assignments The 74LVC1G97 is a single 3-input positive configurable multiple function gate with a standard push-pull output. The output state is determined by eight patterns of 3-bit input. The user can chose the logic functions MUX, AND, OR,
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74LVC1G97
74LVC1G97
DS35127
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