four channel demultiplexer
Abstract: HFDN-10 MAX3831 multiplexer and demultiplexer
Text: Application Note: HFDN-1.0 Rev 0; 5/00 Disabling the Channel-Assignment Feature of the MAX3831 MAXIM High-Frequency/Fiber Communications Group HF-1_V1X.DOC 06/13/00 Maxim Integrated Products Table of Contents I. Overview .1
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MAX3831
-200ps
600ps
four channel demultiplexer
HFDN-10
MAX3831
multiplexer and demultiplexer
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MAX3831
Abstract: No abstract text available
Text: Application Note: HFDN-1.0 Rev.1; 04/08 Disabling the Channel-Assignment Feature of the MAX3831 Maxim Integrated Products Disabling the Channel-Assignment Feature of the MAX3831 SDH/SONET headers. The MAX3831 inverts channel 4 at the multiplexer and then inverts channel 4 again
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MAX3831
MAX3831
200ps
600ps
-200ps
600ps
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Untitled
Abstract: No abstract text available
Text: 19-2718; Rev 2; 4/09 2.488Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier Features The MAX3882A is a deserializer combined with clock and data recovery and limiting amplifier ideal for converting 2.488Gbps serial data to 4-bit-wide, 622Mbps
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488Gbps
MAX3882A
622Mbps
10mVP-P
622Mbps.
155MHz
622MHz
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T3666-2
Abstract: marking code 36L CAZ MARKING ic MARKING FZ sis 650 transistor marking 36L MAX3882 MAX3882EGX
Text: 19-2718; Rev 1; 11/05 2.488Gbps/2.67Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier Features The MAX3882 is a deserializer combined with clock and data recovery and limiting amplifier ideal for converting 2.488Gbps/2.67Gbps serial data to 4-bit-wide,
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488Gbps/2
67Gbps
MAX3882
622Mbps/667Mbps
10mVP-P
622Mbps/667Mbps.
T3666-2
marking code 36L
CAZ MARKING
ic MARKING FZ
sis 650
transistor marking 36L
MAX3882EGX
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hef4051
Abstract: 74AUP2G34 74LVT1403 74ABT543A 74LV74 74AVCH1T45 74HC590 CBTD3306 NCX2200 74HC40103
Text: ロジック IC データスイッチ/アナログスイッチ コンパレータ レベルシフタ 汎用ロジック Index 2 ●● P3 NXP ロジック ●● P4 低抵抗アナログスイッチ/データスイッチ ●● P7 コンパレータ ●●
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sis 650
Abstract: MAX3882 MAX3882EGX
Text: 19-2718; Rev 0; 1/03 2.488Gbps/2.67Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier Features ♦ No Reference Clock Required for Data Acquisition ♦ Input Data Rates: 2.488Gbps or 2.67Gbps ♦ Fully Integrated Clock and Data Recovery with
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488Gbps/2
67Gbps
488Gbps
67Gbps
622Mbps/667Mbps
10mVP-P
50mVP-P
600mVP-P
170mV
sis 650
MAX3882
MAX3882EGX
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sis 650
Abstract: No abstract text available
Text: 19-2718; Rev 2; 4/09 2.488Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier Features The MAX3882A is a deserializer combined with clock and data recovery and limiting amplifier ideal for converting 2.488Gbps serial data to 4-bit-wide, 622Mbps
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488Gbps
MAX3882A
622Mbps
10mVP-P
622Mbps.
155MHz
622MHz
sis 650
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Untitled
Abstract: No abstract text available
Text: 19-5127; Rev 0; 1/10 TION KIT EVALUA BLE A IL A V A SAS/SATA Single Lane 2:1/1:2 Multiplexer/ Demultiplexer Plus Redriver with Equalization The MAX4986 active 2:1/1:2 multiplexer/demultiplexer equalizes and redrives SAS/SATA or SATA-only signals up to 6.0Gbps and operates from a single +3.3V supply.
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MAX4986
T423590
MAX4986
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Untitled
Abstract: No abstract text available
Text: 19-5127; Rev 1; 7/12 TION KIT EVALUA BLE A IL A V A SAS/SATA Single Lane 2:1/1:2 Multiplexer/ Demultiplexer Plus Redriver with Equalization The MAX4986 active 2:1/1:2 multiplexer/demultiplexer equalizes and redrives SAS/SATA or SATA-only signals up to 6.0Gbps and operates from a single +3.3V supply.
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MAX4986
a1/10
MAX4986ETO+
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MAX4986
Abstract: HFAN-08 D10.2 pattern MAX4986CTO
Text: 19-5127; Rev 1; 7/12 TION KIT EVALUA BLE A IL A V A SAS/SATA Single Lane 2:1/1:2 Multiplexer/ Demultiplexer Plus Redriver with Equalization The MAX4986 active 2:1/1:2 multiplexer/demultiplexer equalizes and redrives SAS/SATA or SATA-only signals up to 6.0Gbps and operates from a single +3.3V supply.
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MAX4986
MAX4986ETO+
HFAN-08
D10.2 pattern
MAX4986CTO
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abstract for
Abstract: No abstract text available
Text: submitted to ISSCC’98/communications J. Hauenschild et al. A Two-Chip Receiver for Short Haul Links up to 3.5Gb/s with PIN-Preamp Module and CDR-DMUX Jürgen Hauenschild, Dirk Friedrich, Jürgen Herrle, Joachim Krug Siemens AG, HL HF M SL, P.O.BOX 80 17 09, D-81617 Munich,
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98/communications
D-81617
25GHz
200m98/communications
24dBm)
-20dBm)
ISSCC98-slides
abstract for
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NTE74HC4067
Abstract: NTE4097B NTE74HC299 NTE4017B NTE4007 NTE4023B NTE4027B NTE74HC4053 NTE4553B NTE74HC165
Text: Semiconductors Integrated Circuits Integrated Circuits cont. Part Number Description NTE40175B IC-CMOS, Quad D-Type Flip-Flop NTE4017B IC-CMOS, Decade Counter w/10 Decoder Outputs NTE40182B IC-CMOS, Look Ahead Carry Generator Part Number Description NTE4018B
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NTE40175B
NTE4017B
NTE40182B
NTE4018B
NTE4001B
NTE4019B
NTE4001BT
NTE40192B
NTE4002B
NTE40193B
NTE74HC4067
NTE4097B
NTE74HC299
NTE4017B
NTE4007
NTE4023B
NTE4027B
NTE74HC4053
NTE4553B
NTE74HC165
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TQ8105
Abstract: TQ8106 TQ8106S TQ8105P pip03
Text: R I SONET/SDH Overhead Processor Q U I N T TQ8105 or TQ8106 SONET/SDH Transceiver S E M I C O N D U C T O R, I N C . Rx O/E with CDR Tx O/E Reference Clock TQ8105/8106 PRELIMINARY DATA SHEET SONET/SDH Transceivers TELECOM PRODUCTS T Features SONET/SDH Overhead
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TQ8105
TQ8106
TQ8105/8106
TQ8105/TQ8106
TQ8106
TQ8105
TQ8106S
TQ8105P
pip03
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cdr 03a
Abstract: TQ8105 TQ8106 TQ8105P
Text: R I SONET/SDH Overhead Processor Q U I N T TQ8105 or TQ8106 SONET/SDH Transceiver S E M I C O N D U C T O R, I N C . Rx O/E with CDR Tx O/E Reference Clock TQ8105/8106 PRELIMINARY DATA SHEET SONET/SDH Transceivers TELECOM PRODUCTS T Features SONET/SDH Overhead
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TQ8105
TQ8106
TQ8105/8106
TQ8105/TQ8106
TQ8106
cdr 03a
TQ8105
TQ8105P
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56us
Abstract: OC192 MAX3953 MAX3953UGK MAX3970 MAX3971A PDO11 VCO at 15GHZ PDO15 PDO14
Text: 19-2624; Rev 0; 10/02 10Gbps 1:16 Deserializer with Clock Recovery Features ♦ Serial Data Rate: 9.953Gbps/10.3125Gbps ♦ Clock Recovery with 1:16 Demultiplexer ♦ 0.75UIP-P High-Frequency Jitter Tolerance ♦ 16-Bit Parallel LVDS Output ♦ OIF-Compliant Parallel Interface
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10Gbps
953Gbps/10
3125Gbps
75UIP-P
16-Bit
100mVP-P
MAX3953
rate/64
rate/16
10x10x09
56us
OC192
MAX3953UGK
MAX3970
MAX3971A
PDO11
VCO at 15GHZ
PDO15
PDO14
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SN74ALVCH162245
Abstract: Schottky Barrier Diode Bus-Termination Array SN7400 CLOCKED SLLS210 SCAD001D TEXAS INSTRUMENTS SN7400 SERIES buffer SN74LVCC4245 sn74154 SDAD001C SN7497
Text: Section 4 Logic Selection Guide ABT – Advanced BiCMOS Technology . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3 ABTE/ETL – Advanced BiCMOS Technology/ Enhanced Transceiver Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9
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S8004
Abstract: 8636
Text: VITESSE VS8004/8005 Data Sheet 2.5 Gbits/sec 4-Bit Multiplexer/ Demultiplexer Chipset Features • Serial Data Rates up to 2.5 Gb/s • Differential or Single-Ended Inputs and Outputs • Parallel Data Rates up to 625 Mb/s • Low Power Dissipation: 1.5 W Typ. Per Chip
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VS8004/8005
28-pin
VS8004
VS8005
VS8005:
G52012-0
S8004
8636
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74LS155 dual 24 decoder
Abstract: No abstract text available
Text: MM54HCT155/MM74HCT155 National PRELIMINARY £ 2 Semiconductor MM54HCT155/MM74HCT155 Dual 2-to-4 Line Decoder/Demultiplexers T mlcroCMOS ‘ General Description The MM54HCT155/MM74HCT155 is a high speed silicon gate CMOS decoder/demultiplexer. It features dual 1-to-4
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MM54HCT155/MM74HCT155
MM54HCT155/MM74HCT155
74HCT
Cto85
74LS155 dual 24 decoder
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74AHCT
Abstract: No abstract text available
Text: Zytrex ZXS4AHCT ZX74AHCT Dual 2-to-4 Line Decoder/Multiplexers F e b ru a ry 1 9 8 5 O B J E C T IV E S P E C IF IC A T IO N S 155 . Features Description • Typical applications: Dual 2-to-4 line decoder Dual 1-to-4 line demultiplexer 3-to-8 line decoder
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ZX54AHCT
ZX74AHCT
54/74ALS
74AHCT:
54AHCT:
ahcti55
74AHCT
54AHCT
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HCTLS
Abstract: decoder IC 4 line to 16 line ttl and 74HCTLS 61GL Zytrex BC314
Text: Zyfrex ZX54HCTLS ZX74HCTLS 155 Dual 2-to-4 Line D ecoder/M ultiplexers Februa ry 1985 OBJECTIVE SPECIFICATIONS Description Features • Typical applications: Dual 2-to-4 line decoder Dual 1-to-4 line demultiplexer 3-to-8 line decoder 1-to-8 line demultiplexer
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ZX74HCTLS
54/74LS
74HCTLS:
54HCTLS:
54HCTLS
HCTLS
decoder IC 4 line to 16 line ttl and
74HCTLS
61GL
Zytrex
BC314
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owi 1575
Abstract: C7812 C781 AR1019
Text: IN TE G R A TE D CIRCUITS [nlEET OQ2536HP SDH/SONET STM16/OC48 demultiplexer 1998 M ar 10 P roduct specification File under Integrated C ircuits, IC19 Philips Semiconductors PHILIPS PHILIPS Philips S e m ico nd uctors P ro d u c t specification SDH / S O N E T STM1 6 / 0 C 48 d e mul t i pl e x e r
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OQ2536HP
STM16/OC48
425102/200/01/pp20
owi 1575
C7812
C781
AR1019
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HD b3c
Abstract: No abstract text available
Text: APRIL, 1996 SXT6234 E-Rate Multiplexer General Description Features The SXT6234 E-Rate Multiplexer is a single-chip solution for multiplexing four tributary channels into a single high speed data stream and for demultiplexing a high speed data stream back to four tributary channels. A ll of the necessary
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SXT6234
SXT6234
HD b3c
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SRG8 -led
Abstract: SRG8 Multiplexer SRG4 4046 vco HEF4017 HEF4009 HEF4751V EF4016 HEF4053 pll 4046
Text: FUNCTIONAL DIAGRAMS/ IEC SYM BOLS H EF4 0 0 0 B Dual 3-input NO R gate and inverter. H E F4 0 0 1 U B H EF4001B 3 k yÀ ’ 2 171 V " 5 3 > ^ 6 10 — 3) V 1 h Quadruple 2-input N O R gate. 8 9 3) y * . 11. i Quadruple 2-input N O R gate; unbuffered. H EF4 0 0 2 B
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EF4001B
7Z93167
18-stage
EF4007U
7Z86699
Z83579
EF40245B
EF40373B
EF40374B
SRG8 -led
SRG8 Multiplexer
SRG4
4046 vco
HEF4017
HEF4009
HEF4751V
EF4016
HEF4053
pll 4046
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demultiplexer 1 to 4 outputs HF
Abstract: No abstract text available
Text: MOTOROLA SEMICONDUCTOR TECHNICAL DATA L o w -V o ltag e Q uiet CMOS 1 -o f-8 D ecoder/D em ultiplexer M C74LVQ 138 LVQ The MC74LVQ138 is a high performance, 1-of-8 decoder/ demultiplexer operating from a 2.7 to 3.6V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers
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MC74LVQ138
LVQ138
MC74LVQ138/D
demultiplexer 1 to 4 outputs HF
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