Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    CY7C25552KV18 Search Results

    CY7C25552KV18 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    3M Touch Systems

    Abstract: No abstract text available
    Text: CY7C25402KV18, CY7C25552KV18 CY7C25422KV18, CY7C25442KV18 72-Mbit QDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency with ODT Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions With Read Cycle Latency of 2.0 cycles:


    Original     		PDF CY7C25402KV18, CY7C25552KV18 CY7C25422KV18, CY7C25442KV18 72-Mbit CY7C25402KV18 CY7C25552KV18 CY7C25422KV18 3M Touch Systems

    CY7C25442KV18

    Abstract: CY7C25442KV18-300BZI 78 ball fbga thermal resistance 3M Touch Systems
    Text: CY7C25442KV18 72-Mbit QDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency with ODT Features • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 333 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency


    Original     		PDF CY7C25442KV18 72-Mbit CY7C25442KV18 CY7C25442KV18-300BZI 78 ball fbga thermal resistance 3M Touch Systems

    Untitled

    Abstract: No abstract text available
    Text: CY7C25442KV18 72-Mbit QDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency with ODT 72-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT Features • Separate independent read and write data ports ❐ Supports concurrent transactions


    Original     		PDF CY7C25442KV18 72-Mbit

    neutron

    Abstract: 3M Touch Systems
    Text: CY7C25442KV18 72-Mbit QDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency with ODT 72-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT Features • Separate independent read and write data ports ❐ Supports concurrent transactions


    Original     		PDF CY7C25442KV18 72-Mbit neutron 3M Touch Systems

    Untitled

    Abstract: No abstract text available
    Text: CY7C25442KV18 72-Mbit QDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency with ODT 72-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT Features • Separate independent read and write data ports ❐ Supports concurrent transactions


    Original     		PDF CY7C25442KV18 72-Mbit 333-MHz