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    CQ 1265 Search Results

    CQ 1265 Result Highlights (2)

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    MLC1265-701MLC Coilcraft Inc General Purpose Inductor, 0.7uH, 20%, 1 Element, Iron-Core, SMD, 4541, CHIP, 4541, ROHS COMPLIANT Visit Coilcraft Inc
    MLC1265-701MLB Coilcraft Inc General Purpose Inductor, 0.7uH, 20%, 1 Element, Iron-Core, SMD, 4541, CHIP, 4541, ROHS COMPLIANT Visit Coilcraft Inc
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    CQ 1265 Price and Stock

    onsemi FSCQ1265RTYDTU

    IC OFFLINE SW FLBACK TO220F-5L
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    Newark FSCQ1265RTYDTU Bulk 400
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    TE Connectivity STM02512658PCQ

    Headers & Wire Housings STM02512658PCQ WDUALOBE
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    Mouser Electronics STM02512658PCQ
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    Fairchild Semiconductor Corporation FSCQ1265RTYDTU

    IC SWIT PWM GREEN OVP HV TO220
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    Win Source Electronics FSCQ1265RTYDTU 38
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    CQ 1265 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    CQ 1265

    Abstract: No abstract text available
    Text: GS81302Q08/09/18/36E-333/300/250 333 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O 144Mb SigmaQuadTM-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package


    Original     		PDF GS81302Q08/09/18/36E-333/300/250 165-Bump 165-bump, 144Mb 81302Qxx CQ 1265

    Untitled

    Abstract: No abstract text available
    Text: GS81302Q08/09/18/36E-333/300/250 333 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O 144Mb SigmaQuadTM-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features Clocking and Addressing Schemes • Simultaneous Read and Write SigmaQuad Interface


    Original     		PDF GS81302Q08/09/18/36E-333/300/250 165-Bump 165-bump, 144Mb 81302Qxx

    Untitled

    Abstract: No abstract text available
    Text: GS81302Q08/09/18/36E-333/300/250 144Mb SigmaQuadTM-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 333 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package


    Original     		PDF GS81302Q08/09/18/36E-333/300/250 165-Bump 165-bump, 144Mb 81302Qxx

    Untitled

    Abstract: No abstract text available
    Text: CY7C1310V18 CY7C1312V18 CY7C1314V18 PRELIMINARY 18-Mb QDR -II SRAM 2-Word Burst Architecture Features Functional Description • Separate independent Read and Write data ports — Supports concurrent transactions • 167-MHz clock for high bandwidth • 2-Word Burst on all accesses


    Original     		PDF CY7C1310V18 CY7C1312V18 CY7C1314V18 18-Mb 167-MHz 167MHz

    CQ 1265

    Abstract: 3M Touch Systems
    Text: CY7C1261KV18, CY7C1276KV18 CY7C1263KV18, CY7C1265KV18 36-Mbit QDR II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate independent read and write data ports


    Original     		PDF 36-Mbit CY7C1261KV18, CY7C1276KV18 CY7C1263KV18, CY7C1265KV18 CY7C1261KV18 CY7C1276KV18 CY7C1263KV18 CQ 1265 3M Touch Systems

    Untitled

    Abstract: No abstract text available
    Text: CY7C12611KV18, CY7C12761KV18 CY7C12631KV18, CY7C12651KV18 36-Mbit QDR II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) Features Functional Description • Separate independent read and write data ports


    Original     		PDF CY7C12611KV18, CY7C12761KV18 CY7C12631KV18, CY7C12651KV18 36-Mbit

    3M Touch Systems

    Abstract: No abstract text available
    Text: THIS SPEC IS OBSOLETE Spec No: 001-53193 Spec Title: CY7C12611KV18/CY7C12761KV18/CY7C12631KV18/ CY7C12651KV18, 36-MBIT QDR R II+ SRAM 4-WORD BURST ARCHITECTURE (2.5 CYCLE READ LATENCY) Sunset Owner: Robert Cajustin (AJU) Replaced by: None CY7C12611KV18, CY7C12761KV18


    Original     		PDF Y7C12611KV18/CY7C12761KV18/CY7C12631KV18/ CY7C12651KV18, 36-MBIT CY7C12611KV18, CY7C12761KV18 CY7C12631KV18, CY7C12651KV18 3M Touch Systems

    3M Touch Systems

    Abstract: No abstract text available
    Text: CY7C1261KV18, CY7C1276KV18 CY7C1263KV18, CY7C1265KV18 36-Mbit QDR II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate independent read and write data ports


    Original     		PDF 36-Mbit CY7C1261KV18, CY7C1276KV18 CY7C1263KV18, CY7C1265KV18 CY7C1261KV18 CY7C1276KV18 CY7C1263KV18 3M Touch Systems

    Untitled

    Abstract: No abstract text available
    Text: CY7C1261KV18, CY7C1276KV18 CY7C1263KV18, CY7C1265KV18 36-Mbit QDR II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate independent read and write data ports


    Original     		PDF CY7C1261KV18, CY7C1276KV18 CY7C1263KV18, CY7C1265KV18 36-Mbit CY7C1263KV18

    Untitled

    Abstract: No abstract text available
    Text: CY7C1263KV18/CY7C1265KV18 36-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions


    Original     		PDF CY7C1263KV18/CY7C1265KV18 36-Mbit CY7C1265KV18

    3M Touch Systems

    Abstract: No abstract text available
    Text: CY7C1263KV18, CY7C1265KV18 36-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions


    Original     		PDF CY7C1263KV18, CY7C1265KV18 36-Mbit CY7C1263KV18 3M Touch Systems

    Untitled

    Abstract: No abstract text available
    Text: GS81302Q07/10/19/37E-318/300/250/200 144Mb SigmaQuad-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 clock Latency • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface


    Original     		PDF GS81302Q07/10/19/37E-318/300/250/200 165-Bump 165-bump, 81302Q1937

    Untitled

    Abstract: No abstract text available
    Text: GS81302Q07/10/19/37E-318/300/250/200 144Mb SigmaQuad-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 clock Latency • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface


    Original     		PDF GS81302Q07/10/19/37E-318/300/250/200 144Mb 165-Bump 81302Q1937

    GS81302Q37GE-333

    Abstract: No abstract text available
    Text: GS81302Q07/10/19/37E-333/300/250/200 144Mb SigmaQuad-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 333 MHz–200 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • 2.0 clock Latency • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package


    Original     		PDF GS81302Q07/10/19/37E-333/300/250/200 165-Bump 165-bump, 81302Q1937 GS81302Q37GE-333

    d33 02C

    Abstract: No abstract text available
    Text: GS81302Q07/10/19/37E-318/300/250/200 144Mb SigmaQuad-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 clock Latency • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface


    Original     		PDF GS81302Q07/10/19/37E-318/300/250/200 165-Bump 165-bump, avai0/250/200 81302Q1937 d33 02C

    Untitled

    Abstract: No abstract text available
    Text: CY7C1263XV18/CY7C1265XV18 36-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate Independent Read and Write Data Ports


    Original     		PDF CY7C1263XV18/CY7C1265XV18 36-Mbit CY7C1265XV18

    Untitled

    Abstract: No abstract text available
    Text: GS81302QT07/10/19/37E-318/300/250/200 144Mb SigmaQuad-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 clock Latency • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface


    Original     		PDF GS81302QT07/10/19/37E-318/300/250/200 144Mb 165-Bump 81302QT1937E

    CQ 1265

    Abstract: AN1021
    Text: GS81302QT07/10/19/37E-333/300/250/200 144Mb SigmaQuad-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 clock Latency • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface


    Original     		PDF GS81302QT07/10/19/37E-333/300/250/200 144Mb 165-Bump 165-bump, GS81302QTxxE-300T. 81302QT1937E CQ 1265 AN1021

    3M Touch Systems

    Abstract: No abstract text available
    Text: CY7C1263XV18, CY7C1265XV18 36-Mbit QDR II+ Xtreme SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit QDR® II+ Xtreme SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate Independent Read and Write Data Ports


    Original     		PDF 36-Mbit CY7C1263XV18, CY7C1265XV18 CY7C1263XV18 3M Touch Systems

    GS81302QT19GE-200

    Abstract: No abstract text available
    Text: GS81302QT07/10/19/37E-333/300/250/200 144Mb SigmaQuad-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 333 MHz–200 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • 2.0 clock Latency • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package


    Original     		PDF GS81302QT07/10/19/37E-333/300/250/200 165-Bump 165-bump, GS81302QTxxE-300T. 81302QT1937E GS81302QT19GE-200

    GS81302QT07E-300

    Abstract: No abstract text available
    Text: GS81302QT07/10/19/37E-318/300/250/200 144Mb SigmaQuad-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 clock Latency • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface


    Original     		PDF GS81302QT07/10/19/37E-318/300/250/200 165-Bump 165-bump, 81302QT1937E GS81302QT07E-300

    Untitled

    Abstract: No abstract text available
    Text: CY7C1263XV18, CY7C1265XV18 36-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Configurations Features Separate Independent Read and Write Data Ports


    Original     		PDF CY7C1263XV18, CY7C1265XV18 36-Mbit

    3M Touch Systems

    Abstract: No abstract text available
    Text: CY7C1263XV18, CY7C1265XV18 36-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate Independent Read and Write Data Ports


    Original     		PDF CY7C1263XV18, CY7C1265XV18 36-Mbit CY7C1263XV18 3M Touch Systems

    Untitled

    Abstract: No abstract text available
    Text: 10 NO TES: 1. HOUSING M A T E R IA L : LC P , G L A S S F IL L E D , U L 9 4 V - 0 COLOUR B L A C K . - .0 4 4 1 .0 0 3 (1.12 ± 0.08 .0 7 9 2 . 00 ) 2. T E R M IN A L M A T E R IA L : P H O S P H O R BR O N ZE 3 . S E E A P P R O P R IA T E S H E E T FO R CIRCUIT S IZE ,


    OCR Scan     		PDF