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    BUS DOOR Search Results

    BUS DOOR Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    CS-USB3.1TYPC-001M Amphenol Cables on Demand Amphenol CS-USB3.1TYPC-001M Amphenol Premium USB 3.1 Gen2 Certified USB Type A-C Cable - USB 3.0 Type A Male to Type C Male [10.0 Gbps SuperSpeed] 1m (3.3ft) Datasheet
    CS-USBAM003.0-001 Amphenol Cables on Demand Amphenol CS-USBAM003.0-001 Amphenol Premium USB 3.0/3.1 Gen1 Certified USB Type A-A Cable - USB 3.0 Type A Male to Type A Male [5.0 Gbps SuperSpeed] 1m (3.3') Datasheet
    CS-USBAB003.0-002 Amphenol Cables on Demand Amphenol CS-USBAB003.0-002 Amphenol Premium USB 3.0/3.1 Gen1 Certified USB Type A-B Cable - USB 3.0 Type A Male to Type B Male [5.0 Gbps SuperSpeed] 2m (6.6') Datasheet
    CS-USBAB003.0-001 Amphenol Cables on Demand Amphenol CS-USBAB003.0-001 Amphenol Premium USB 3.0/3.1 Gen1 Certified USB Type A-B Cable - USB 3.0 Type A Male to Type B Male [5.0 Gbps SuperSpeed] 1m (3.3') Datasheet
    CS-USBAM003.0-002 Amphenol Cables on Demand Amphenol CS-USBAM003.0-002 Amphenol Premium USB 3.0/3.1 Gen1 Certified USB Type A-A Cable - USB 3.0 Type A Male to Type A Male [5.0 Gbps SuperSpeed] 2m (6.6') Datasheet

    BUS DOOR Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    "printer controller"

    Abstract: 486 system bus 6502 CPU door bell AB-2061G-33 MO-112 RH15
    Text: AB-2061G-33 33Mhz PCI to Local Bus Interface for 8 or 16 bit Local Bus Applications 32- to 16- bit PCI to local bus translator AB-2061-33 33Mhz PCI to Local Bus Interface Product Specification AB Semicon AB-2061-33 32 bit to 8 or 16 bit PCI to local bus translator


    Original     		PDF AB-2061G-33 33Mhz AB-2061-33 "printer controller" 486 system bus 6502 CPU door bell AB-2061G-33 MO-112 RH15

    doorbell application

    Abstract: la2 d2 timer PIN CONFIGURATION pci 32 bit 5 v PCI9060ES PCI9060SD 10B5 9060ES 93CS56 NM93CS46
    Text: PCI 9060ES November 1995 PCI Bus Master Interface Chip for VERSION 1.0 Adapters and Embedded Systems Features_ • • • • PCI Bus Master and Bus Slave transfers up to 132


    Original     		PDF 9060ES 100ns 150ns 200ns 250ns 300ns 350ns 400ns 450ns A31-29 doorbell application la2 d2 timer PIN CONFIGURATION pci 32 bit 5 v PCI9060ES PCI9060SD 10B5 9060ES 93CS56 NM93CS46

    9060ES

    Abstract: PCI9060ES PCI9060SD small endian AD-1508
    Text: PCI 9060ES November 1995 PCI Bus Master Interface Chip for VERSION 1.0 Adapters and Embedded Systems Features_ • • • • PCI Bus Master and Bus Slave transfers up to 132


    Original     		PDF 9060ES PCI9060ES PCI9060SD PCI9060ES 9060ES small endian AD-1508

    NM93CS46

    Abstract: PCI9060ES PCI9060SD 10B5 9060ES 93CS56
    Text: PCI 9060ES November 1995 PCI Bus Master Interface Chip for VERSION 1.0 Adapters and Embedded Systems Features_ • • • • PCI Bus Master and Bus Slave transfers up to 132


    Original     		PDF 9060ES 100ns 150ns 200ns 250ns 300ns 350ns 400ns 450ns A31-29 NM93CS46 PCI9060ES PCI9060SD 10B5 9060ES 93CS56

    UAA2022

    Abstract: Circuit UAA2022 Nippon Car central Locking car wiring system for central locking uaa2022 led driver IC 741 as zero sequence detector AN-475 datasheet UAA2022 download AUTOMATIC STREET LIGHT CONTROLLER USING IC PROTOCOL AN475
    Text: Order this document as AN475/D MOTOROLA SEMICONDUCTOR APPLICATION NOTE AN475 Single wire MI Bus controlling stepper motors by Michel Burri & Dr. Pascal Renard Senior Staff engineers, Automotive Group Motorola SA, Geneva 1. Introduction The Motorola Interconnect Bus MI Bus is a serial bus and communications protocol which efficiently


    Original     		PDF AN475/D AN475 UAA2022 Circuit UAA2022 Nippon Car central Locking car wiring system for central locking uaa2022 led driver IC 741 as zero sequence detector AN-475 datasheet UAA2022 download AUTOMATIC STREET LIGHT CONTROLLER USING IC PROTOCOL AN475

    PCF85063A

    Abstract: PCA9541A
    Text: I2C-bus Components Selection Guide I2C-bus Components Selection Guide Overview TABLE OF CONTENTS Overview . . . . . . . . . . . . . . . . 1 I2C-bus System Diagram . . . . 2 General Purpose Input Output GPIO Expanders . . . 3 Thermal Sensors and Voltage Management . . . . . . 6


    Original     		PDF

    amcc part marking

    Abstract: AMCC S5335 S5335QFAAB AMCC DATE CODE MARKING "serial nvram" S5335 K10101A nv ram data sheet pic 92121 s5935
    Text: Part Number S5335 Revision 5.01 – November 30, 2005 S5335 Data Sheet PCI Bus Controller, 3.3V S5335 PCI BUS CONTROLLER MATCH MAKER AMCC Confidential and Proprietary DS1657 Revision 5.01 – November 30, 2005 S5335 – PCI Bus Controller, 3.3V Data Sheet


    Original     		PDF S5335 DS1657 amcc part marking AMCC S5335 S5335QFAAB AMCC DATE CODE MARKING "serial nvram" S5335 K10101A nv ram data sheet pic 92121 s5935

    V363EPC

    Abstract: V363EPC-50LPA0 29030 V380SDC V96BMC V96SSC
    Text: V363EPC ENHANCED PCI BRIDGE CONTROLLER For 32-bit Multiplexed/Demultiplexed Address/Data Bus Fully compliant with PCI Local Bus Specification, Revision 2.1 Configurable for system master, PCI master, or PCI target operation 32-bit, 33 MHz PCI bus interface


    Original     		PDF V363EPC 32-bit 32-bit, 401TM 2348G TB-EC63-0200 V363EPC V363EPC-50LPA0 29030 V380SDC V96BMC V96SSC

    PIN CONFIGURATION pci 32 bit 5 v

    Abstract: 9060ES 9060SD RC32364 RC5000 pci 32 bit 5 v
    Text: Support Components PLX Technology Inc. PCI 9080 I2O Compatible PCI Bus Master I/O Accelerator Chip Features Description ◆ PCI Version 2.1 compliant Bus Master interface chip for adapters and embedded systems ◆ Programmable local bus supports nonmultiplexed 32-bit


    Original     		PDF 32-bit 16-bit, PIN CONFIGURATION pci 32 bit 5 v 9060ES 9060SD RC32364 RC5000 pci 32 bit 5 v

    9060ES

    Abstract: 9060SD MPC860 9985K
    Text: PCI 9080 I2O Compatible PCI Bus Master I/O Accelerator Chip Features • PCI Version 2.1 compliant Bus Master interface chip for adapters and embedded systems ■ Programmable local bus supports nonmultiplexed 32-bit address/data, multiplexed 32- or 16-bit, and


    Original     		PDF 32-bit 16-bit, 208-pin 133MB/sec 32-bi960 9080-PB-010 9060ES 9060SD MPC860 9985K

    9060ES

    Abstract: A236
    Text: Use of A236 Parallel Video DSP Chip with a PCI Bus Application Note: Use of A236 Parallel Video DSP Chip with a PCI Bus Revised February 3, 1999 1. Summary This Application Note explains how to connect an A236 Chip to a single PCI bus. The PCI originally named the Peripheral Component Interconnect bus is widely used in many computer


    Original     		PDF 9060ES. 9060ES 9060ES, A236

    9060ES

    Abstract: 9060SD MPC860
    Text: PCI 9080 I2O Compatible PCI Bus Master I/O Accelerator Chip Features • PCI Version 2.1 compliant Bus Master interface chip for adapters and embedded systems ■ Programmable local bus supports nonmultiplexed 32-bit address/data, multiplexed 32- or 16-bit, and


    Original     		PDF 32-bit 16-bit, 208-pin 133MB/sec 32-bitel 9080-PB-010 9060ES 9060SD MPC860

    doorbell application

    Abstract: doorbell circuit application doorbell PCI I/O 9060ES 9060SD Intel i960 intel i960 series PCI9060
    Text: PCI PLX TECHNOLOGY PCI 9060 • ■ ■ ■ ■ ■ ■ PCI Bus Master Interface Supporting i960 Microprocessor Based Adapters and Systems Two Independent DMA Channels For Local Bus Memory to PCI Host Bus Data Transfers Four Bidirectional FIFOs For Zero


    Original     		PDF 32-Bit 32-Bit 208-Pin 9060SD 9060ES 9060ES. doorbell application doorbell circuit application doorbell PCI I/O 9060ES Intel i960 intel i960 series PCI9060

    MPC860

    Abstract: No abstract text available
    Text: PCI 9054 PCI Bus Master I/O Accelerator Chip Highlights • PCI v2.2 compliant 32-bit 33MHz Bus Master Interface Controller enables PCI Burst Transfers up to 132Mbytes/second ■ General Purpose Bus Master Interface featuring an advanced Data Pipe Architecture which


    Original     		PDF 32-bit 33MHz 132Mbytes/second MPC860 9054-SIL-PB-P2-2

    PCI 9656 schematic

    Abstract: MPC860 RC32364
    Text: VERSION 1.0 2002 PCI 9056 Connectivity 32-bit, 66MHz PCI Bus Mastering I/O Accelerator for Motorola PowerQUICC and Generic 32-bit, 66MHz Local Bus Designs • 32-bit, 66MHz PCI r2.2 compliant ■ Motorola PowerQUICC and generic 32-bit, 66MHz local bus


    Original     		PDF 32-bit, 66MHz 32-bit 256-ball, PCI 9656 schematic MPC860 RC32364

    AV96JA0330420

    Abstract: V350EPC V350EPC-33LPA1 V350EPC-40LPA1 V380SDC V96BMC V96SSC PCI bridge
    Text: V350EPC ENHANCED PCI BRIDGE CONTROLLER For 32-bit Multiplexed Address/Data Bus Fully compliant with PCI Local Bus Specification, Revision 2.1 Configurable for system master, PCI master, or PCI target operation 32-bit, 33 MHz PCI bus interface Direct interface to Intel i960®


    Original     		PDF V350EPC 32-bit 32-bit, 401TM 2348G TB-EC50-0200 AV96JA0330420 V350EPC V350EPC-33LPA1 V350EPC-40LPA1 V380SDC V96BMC V96SSC PCI bridge

    PCI 9656 schematic

    Abstract: MPC860 RC32364
    Text: VERSION 1.0 2002 PCI 9056 Connectivity 32-bit, 66MHz PCI Bus Mastering I/O Accelerator for Motorola PowerQUICC and Generic 32-bit, 66MHz Local Bus Designs • 32-bit, 66MHz PCI r2.2 compliant ■ Motorola PowerQUICC and generic 32-bit, 66MHz local bus


    Original     		PDF 32-bit, 66MHz 32-bit 256-ball, PCI 9656 schematic MPC860 RC32364

    PC107A

    Abstract: microprocessor PC107
    Text: PC107A PCI Bridge Memory Controller Datasheet Features • Processor Bus Frequency up to 100 MHz • 64- or 32-bit Data Bus and 32-bit Address Bus • Provides Support for Either Asynchronous SRAM, Burst SRAM, or Pipelined Burst SRAM Compliant with PCI Specification, Revision 2.1


    Original     		PDF PC107A 32-bit 0842E PC107A microprocessor PC107

    Untitled

    Abstract: No abstract text available
    Text: SECTION 1 GENERAL DESCRIPTION 1. SECTION 1 - PCI 9060 GENERAL DESCRIPTION The PCI9060 is a PCI bus master interface chip that connects a PCI host bus to three local bus types, selected through mode pins. Each local bus configuration matches the protocol of an Intel 80960 processor, but the PCI 9060 may be


    OCR Scan     		PDF PCI9060 PCI9060

    Untitled

    Abstract: No abstract text available
    Text: PCI 9060 * E PCI Bus Master Interface Chip for Adapters and Embedded Systems December, 1995 VERSION 1.2 Features General Description_ • PCI Bus Master Interface supporting adapters and embedded systems • Two independent DMA channels for local bus


    OCR Scan     		PDF PCI9060 100Version 00Q07 PCI9060

    Untitled

    Abstract: No abstract text available
    Text: V292PBC S LOCAL BUS TO PCI BRIDGE FOR DE-MULTIPLEXED A/D PROCESSORS • Glueless interface between AMD’s Am29030/ 40 processors and PCI bus • Fully compliant with PCI 2.1 specification • Configurable for primary master, bus master, or target operation


    OCR Scan     		PDF V292PBC Am29030/ 234SG

    Untitled

    Abstract: No abstract text available
    Text: V961PBC Rev. B2 LOCAL BUS TO PCI BRIDGE FOR MUTLTELEXED A/D PROCESSORS • Glueless interface between Intel ¡960Jx, IBM PPC401Gx, processors and PCI bus • Fully compliant with PCI 2.1 specification • Configurable for primary master, bus master, or target operation


    OCR Scan     		PDF V961PBC 960Jx, PPC401Gx, 8/16-bit V961PBC 234SG

    Untitled

    Abstract: No abstract text available
    Text: V962PBC S LOCAL BUS TO PCI BRIDGE FOR DE-MULTIPLEXED A/D PROCESSORS • Glueless interface between Intel ¡960 Cx/Hx processors and PCI bus • Fully compliant with PCI 2.1 specification • Configurable for primary master, bus master, or target operation


    OCR Scan     		PDF V962PBC 234SG

    S5933QE

    Abstract: Intel 8237 dma controller block diagram AMI eeprom bios amcc s5933 S593X ami bios EMB4 24C04 24C08 256X8
    Text: A MCC ARCHITECTURAL OVERVIEW S5933 INTRODUCTION TO THE PCI LOCAL BUS FEATURES The local bus concept was developed to break the PC data bottleneck. Traditional PC bus architectures are inadequate to m eet the demands of today's graphics-oriented system s and large application


    OCR Scan     		PDF S5933 GD0574Ã S5933QE Intel 8237 dma controller block diagram AMI eeprom bios amcc s5933 S593X ami bios EMB4 24C04 24C08 256X8