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    MMC-SD-SDDMF-0095B-KINGFONT

    Abstract: TFT-G240320LTSW-118W-E BD557 1376408-1 MINI_USB-AB p231d X192 J4G3 MINI-USB-AB Kingfont
    Text: GND 2k RESET_IN V3A VREF P0.10-TXD2 P0.12-PORT-PWR-B P0.18-MOSI P0.22 P0.26-AOUT P1.3-MCICMD P1.11-MCIDAT2 P1.19 P1.23-LCDVD13 BDQM1 BCAS BBLS1 BWE BA23 BA21 BA19 BA17 P3.31-BD31 P3.29-PWM1.6-BD29 P3.27-PWM1.4-BD27 P3.25-PWM1.2-BD25 P3.23-BD23 P3.21-DTR1-BD21


    Original     		PDF 1N4148 22uF/10V 33F/5 FDV303N 10-EINT0 11-LCDCLKIN 8-LCDVD16 28-SCL-A-LCDVD22 29-SDA-A-LCDVD23 15-SCK MMC-SD-SDDMF-0095B-KINGFONT TFT-G240320LTSW-118W-E BD557 1376408-1 MINI_USB-AB p231d X192 J4G3 MINI-USB-AB Kingfont

    Untitled

    Abstract: No abstract text available
    Text: WED9LAPC2B16P8BC 4M x 32 SDRAM / 2M x 8 SDRAM External Memory Solution for Lucent’s LUCTAPC640 ATM Port Controller FEATURES DESCRIPTION • Clock speeds: • SDRAM: 100 MHz The WED9LAPC2B16P8BC is a 3.3V, 4M x 32 Synchronous DRAM and a 2M x 8 Synchronous DRAM array packaged in a


    Original     		PDF WED9LAPC2B16P8BC LUCTAPC640 WED9LAPC2B16P8BC WED9LAPC2B16P8BI

    M39P0R1080E4

    Abstract: M39P0R9080E4 M58PR001LE M58PR512LE M39P0R09080E4 BCAS SD
    Text: M39P0R9080E4 M39P0R1080E4 512 Mb or 1 Gb x16, multiple bank, multilevel, burst Flash memory 256 Mbit low power SDRAM, 1.8 V supply, multichip package Features • ■ Multichip package – 1 die of 512 Mbit (32 Mb x16) or 1 Gbit (64 Mb ×16) multiple bank, multilevel, burst)


    Original     		PDF M39P0R9080E4 M39P0R1080E4 TFBGA165 64-bit M39P0R1080E4 M39P0R9080E4 M58PR001LE M58PR512LE M39P0R09080E4 BCAS SD

    TAPC640

    Abstract: WED9LAPC2B16P8BC WED9LAPC2C16V4BC
    Text: WED9LAPC2B16P8BC 4M x 32 SDR AM / 2M x 8 SDR AM SDRAM SDRAM EXTERNAL MEMORY SOLUTION FOR AGERE’S TTAPC640 APC640 A TM PORT CONTROLLER ATM DESCRIPTION FEATURES n Clock speeds: The WED9LAPC2B16P8BC is a 3.3V, 4M x 32 Synchronous DRAM and a 2M x 8 Synchronous DRAM array packaged in


    Original     		PDF WED9LAPC2B16P8BC TAPC640 WED9LAPC2B16P8BC WED9LAPC2C16V4BC, APC2B16P8BC WED9LAPC2C16V4BC

    QE R549

    Abstract: qe r542 QE R745 Qe R532 qe R610 QE R528 QE R732 EV-64120 QE R552 LEVEL1-LXT970
    Text: EV-48004A-24 Evaluation Board for the GT-48004A Preliminary Revision 1.0ip 4/13/98 http://www.galileoT.com [email protected] Tel 408 367-1400 Fax (408)367-1401 EV-48004A-24 Evaluation Board for the GT-48004A 1. Introduction The EV-48004A-24 Evaluation Board for the GT-48004A implements a 24-port 10/100 Ethernet switch in a formfactor


    Original     		PDF EV-48004A-24 GT-48004A EV-48004A-24 GT-48004A 24-port 100Mbps QE R549 qe r542 QE R745 Qe R532 qe R610 QE R528 QE R732 EV-64120 QE R552 LEVEL1-LXT970

    Untitled

    Abstract: No abstract text available
    Text: 128MB, 256MB Registered DIMM SDRAM SDRAM Registered Module 168pin Registered Module based on 128Mb F-die with 72-bit ECC Revision 1.0 January. 2004 Rev. 1.0 January. 2004 128MB, 256MB Registered DIMM SDRAM Revision History Revision 0.0 December, 2003 - First release


    Original     		PDF 128MB, 256MB 168pin 128Mb 72-bit

    TAPC640

    Abstract: WED9LAPC2B16P8BC WED9LAPC2C16V4BC b-cas 153 tss
    Text: White Electronic Designs WED9LAPC2B16P8BC 4M x 32 SDRAM / 2M x 8 SDRAM EXTERNAL MEMORY SOLUTION FOR AGERE’S TAPC640 ATM PORT CONTROLLER FEATURES DESCRIPTION Clock speeds: The WED9LAPC2B16P8BC is a 3.3V, 4M x 32 Synchronous DRAM and a 2M x 8 Synchronous DRAM array packaged


    Original     		PDF WED9LAPC2B16P8BC TAPC640 WED9LAPC2B16P8BC WED9LAPC2C16V4BC, WED9LAPC2C16P8BC WED9LAPC2C16P8BI WED9LAPC2C16V4BC b-cas 153 tss

    K4S280432E

    Abstract: M390S1723ET1-C7A M390S1723ETU-C7A M390S3320ET1-C7A M390S3320ETU-C7A M390S3323ET1-C7A
    Text: 128MB, 256MB Registered DIMM SDRAM SDRAM Registered Module 168pin Registered Module based on 128Mb E-die with 72-bit ECC Revision 1.3 February. 2004 Rev. 1.3 February. 2004 128MB, 256MB Registered DIMM SDRAM Revision History Revision 1.0 November, 2002 - First release


    Original     		PDF 128MB, 256MB 168pin 128Mb 72-bit K4S280432E M390S1723ET1-C7A M390S1723ETU-C7A M390S3320ET1-C7A M390S3320ETU-C7A M390S3323ET1-C7A

    B1A12

    Abstract: No abstract text available
    Text: 128MB, 256MB Registered DIMM Preliminary SDRAM SDRAM Registered Module 168pin Registered Module based on 128Mb F-die with 72-bit ECC Revision 0.0 December. 2003 Rev. 0.0 December. 2003 128MB, 256MB Registered DIMM Preliminary SDRAM Revision History Revision 0.0 December, 2003


    Original     		PDF 128MB, 256MB 168pin 128Mb 72-bit B1A12

    Untitled

    Abstract: No abstract text available
    Text: 128MB, 256MB Registered DIMM SDRAM SDRAM Registered Module 168pin Registered Module based on 128Mb F-die with 72-bit ECC Revision 1.3 May 2004 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 1.3 May 2004 128MB, 256MB Registered DIMM


    Original     		PDF 128MB, 256MB 168pin 128Mb 72-bit

    K4S280432F

    Abstract: M390S1723FT1-C7A M390S1723FTU-C7A M390S3320FT1-C7A M390S3320FTU-C7A M390S3323FT1-C7A b-cas
    Text: 128MB, 256MB Registered DIMM SDRAM SDRAM Registered Module 168pin Registered Module based on 128Mb F-die with 72-bit ECC Revision 1.1 February 2004 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 1.1 February 2004


    Original     		PDF 128MB, 256MB 168pin 128Mb 72-bit K4S280432F M390S1723FT1-C7A M390S1723FTU-C7A M390S3320FT1-C7A M390S3320FTU-C7A M390S3323FT1-C7A b-cas

    js83

    Abstract: 28f040 JS98 edo dram 72-pin simms 64mb JS108 JS-105 74LS373SC JS31-JS32 JS107 BYU25
    Text: 32-bit i960Jx Galileo-5 Evaluation & Development Preliminary May 96, Rev. 1.0 System NOTE: Always contact Galileo Technology for possible updates before starting a design. FEATURES • Flexible evaluation, benchmark, software, and hardware development system for the GT-32090 System


    Original     		PDF 32-bit i960Jx GT-32090 MON960) i960Jx 33MHz 16MHz 66MHz js83 28f040 JS98 edo dram 72-pin simms 64mb JS108 JS-105 74LS373SC JS31-JS32 JS107 BYU25

    K4S280432E

    Abstract: M390S1723ET1-C7A M390S1723ETU-C7A M390S3320ET1-C7A M390S3320ETU-C7A M390S3323ET1-C7A
    Text: 128MB, 256MB Registered DIMM SDRAM SDRAM Registered Module 168pin Registered Module based on 128Mb E-die x4, x8 1,700 / 1,500 / 1,200mil Height & 72-bit ECC Revision 1.1 May. 2003 Rev. 1.1 May. 2003 128MB, 256MB Registered DIMM SDRAM Revision History Revision 1.0 (Nov., 2002)


    Original     		PDF 128MB, 256MB 168pin 128Mb 200mil 72-bit K4S280432E M390S1723ET1-C7A M390S1723ETU-C7A M390S3320ET1-C7A M390S3320ETU-C7A M390S3323ET1-C7A

    D12U

    Abstract: No abstract text available
    Text: M377S6428MT1 PC100 Registered DIMM Revision History Revision 0.1 April 29, 2000 - Added the description of " Staktek’s stacking technology is Samsung’s stacking technology of choice." Rev. 0.1 Apr. 2000 M377S6428MT1 PC100 Registered DIMM M377S6428MT1 SDRAM DIMM (Intel 1.0 ver. Base)


    Original     		PDF M377S6428MT1 PC100 M377S6428MT1 64Mx72 64Mx4, 64Mx4 D12U

    M390S3253HU1

    Abstract: No abstract text available
    Text: 256MB, 512MB Registered DIMM SDRAM SDRAM Registered Module 168pin Registered Module based on 256Mb H-die 54 TSOP-II with Pb-Free RoHS compliant INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE.


    Original     		PDF 256MB, 512MB 168pin 256Mb 64Mx4 K4S560432H PC133 M390S3253HU1

    CDC2510A

    Abstract: KMM375S6427T-GL KMM375S6427T-G0 KMM375S6427T-G8 KMM375S6427T-GH
    Text: Preliminary KMM375S6427T SDRAM MODULE KMM375S6427T SDRAM DIMM 64Mx72 SDRAM DIMM with PLL & Register based on Stacked 64Mx4, 4Banks 4K Ref., 3.3V SDRAMs with SPD GENERAL DESCRIPTION FEATURE The Samsung KMM375S6427T is a 64M bit x 72 Synchronous Dynamic RAM high density memory module. The Samsung KMM375S6427T consists of eighteen CMOS Stacked


    Original     		PDF KMM375S6427T KMM375S6427T 64Mx72 64Mx4, 64Mx4 400mil 18-bits 24-pin CDC2510A KMM375S6427T-GL KMM375S6427T-G0 KMM375S6427T-G8 KMM375S6427T-GH

    b1a12

    Abstract: No abstract text available
    Text: White Electronic Designs WV3DG72256V-AD2 PRELIMINARY 2GB – 2x128Mx72 SDRAM, REGISTERED FEATURES DESCRIPTION „ Burst Mode Operation „ Auto and Self Refresh capability „ LVTTL compatible inputs and outputs „ Serial Presence Detect with EEPROM „ Fully synchronous: All signals are registered on the


    Original     		PDF 2x128Mx72 WV3DG72256V-AD2 WV3DG72256V 256Mx4 128Mx4) 100MHz 133MHz b1a12

    CDC2510A

    Abstract: KMM377S3227BT1-GL MA2180
    Text: SDRAM MODULE Preliminary KMM377S3227BT1 Revision History Revision 4 May 1998 - CLK Input Cap. is added by PLL Input Cap. (27pF) Revision 5 (July 1998) - "REGE" description is changed. REV. 5 July 1998 Preliminary KMM377S3227BT1 SDRAM MODULE KMM377S3227BT1 SDRAM DIMM (Intel 1.0 ver. Base)


    Original     		PDF KMM377S3227BT1 KMM377S3227BT1 32Mx72 32Mx4, 32Mx4 400mil 18-bits CDC2510A KMM377S3227BT1-GL MA2180

    CDC2509

    Abstract: MA2180
    Text: SDRAM MODULE Preliminary KMM377S3227BT Revision History Revision .2 Jan. 1998 •DC Characteristics values are changed. : ICC2 N & ICC3 N •STANDARD TIMING DIAGRAM is changed . •All AC parameters are measured by module tap reference(refer to page#5) •CAS Latency is based on Reg. DIMM (In case of Unbuff. DIMM CAS Latency is 1 CLK earlier than this)


    Original     		PDF KMM377S3227BT 200mA. 100Min 540Min) 250Max 35Max) 010Max 32Mx4 KM44S32037BT CDC2509 MA2180

    N3 3kv SEC

    Abstract: N10 3Kv sec N10 3Kv 74HCT595 ALED12 DLED11 EPM7128S-100 LXT970 FLED11 ELED11
    Text: A B C D E MAIN-CFG JTAG&TEST PAL A[3:0] +12V -12V IntF~ IdSelF[1:0] GntF[1:0] ReqF[1:0] 25M-A[7:0] 25M-B[7:0] 25M-A[7:0] 25M-B[7:0] +12V -12V idself[1:0] gntf[1:0] reqf[1:0] intd idsele[1:0] gnte[1:0] reqe[1:0] idseld[1:0] gntd[1:0] reqd[1:0] rst~ rst clk1


    Original     		PDF 25M-A 25M-B N3 3kv SEC N10 3Kv sec N10 3Kv 74HCT595 ALED12 DLED11 EPM7128S-100 LXT970 FLED11 ELED11

    WV3DG72256V-AD2

    Abstract: b1a12
    Text: White Electronic Designs WV3DG72256V-AD2 PRELIMINARY 2GB – 2x128Mx72 SDRAM, REGISTERED FEATURES DESCRIPTION Burst Mode Operation The WV3DG72256V is a 2x128Mx72 synchronous DRAM module which consists of eighteen 256Mx4 stack SDRAM components stacked from 128Mx4 in TSOP II package,


    Original     		PDF WV3DG72256V-AD2 2x128Mx72 WV3DG72256V 256Mx4 128Mx4) 100MHz 133MHz WV3DG72256V-AD2 b1a12

    CDC2510A

    Abstract: KMM377S6427T1GL
    Text: SDRAM MODULE Preliminary KMM377S6427T1 Revision History Revision 3 May 1998 - CLK Input Cap. is added by PLL Input Cap. (27pF) Revision 4 (July 1998) - "REGE" description is changed. REV. 4 July 1998 Preliminary KMM377S6427T1 SDRAM MODULE KMM377S6427T1 SDRAM DIMM (Intel 1.0 ver. Base)


    Original     		PDF KMM377S6427T1 KMM377S6427T1 64Mx72 64Mx4, 64Mx4 400mil 18-bits CDC2510A KMM377S6427T1GL

    PC133 registered reference design

    Abstract: No abstract text available
    Text: M390S3320BT1 PC133 Registered DIMM Revision History Revision 0.0 Sep. 1999 • PC133 first published REV. 0 Sep. 1999 PC133 Registered DIMM M390S3320BT1 M390S3320BT1 SDRAM DIMM 32Mx72 SDRAM DIMM with PLL & Register based on 32Mx4, 4Banks 4K Ref., 3.3V Synchronous DRAMs with SPD


    Original     		PDF M390S3320BT1 PC133 M390S3320BT1 32Mx72 32Mx4, PC133 registered reference design

    CDC2509

    Abstract: Intel 1.2 ver Base M377S3253AT3 M377S3253AT3-C1H M377S3253AT3-C1L
    Text: M377S3253AT3 PC100 Registered DIMM Revision History Revision 0.0 Oct.13, 1999 Rev. 0.0 Oct.1999 PC100 Registered DIMM M377S3253AT3 M377S3253AT3 SDRAM DIMM (Intel 1.2 ver Base) 32Mx72 SDRAM DIMM with PLL & Register based on 32Mx8, 4Banks 8K Ref., 3.3V Synchronous DRAMs with SPD


    Original     		PDF M377S3253AT3 PC100 M377S3253AT3 32Mx72 32Mx8, 32Mx8 CDC2509 Intel 1.2 ver Base M377S3253AT3-C1H M377S3253AT3-C1L