CI 74LS00
Abstract: Automatic Load Sharing between Two or More Transf CI 74LS148
Text: ViewDraw User’s Guide Spring 2000 Copyright Page Copyright 1985, 1996, 1997, 1998, 1999, 2000 Innoveda, Inc. 293 Boston Post Road West Marlboro, Massachusetts 01752–4615 All Rights Reserved. This information is copyrighted; all rights are reserved by Innoveda, Inc. This information may
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NEC uPD7210
Abstract: 68172 tca 785 cp VME bus controller GPIB-1014 GPIB1014D HD68450 IEEE488 MC68450 PD7210
Text: GPIB-1014D User Manual March 1997 Edition Part Number 320140-01 Copyright 1990, 1997 National Instruments Corporation. All Rights Reserved. National Instruments Corporate Headquarters 6504 Bridge Point Parkway Austin, TX 78730-5039 512 794-0100 Technical support phone: (512) 795-8248
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GPIB-1014D
Index-19
GPIB-1014D
PD7210
Index-20
NEC uPD7210
68172
tca 785 cp
VME bus controller
GPIB-1014
GPIB1014D
HD68450
IEEE488
MC68450
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IEEE Standard 1014-1987
Abstract: NEC uPD7210 F1241 LS2521 GPIB-1014 HD68450 MC68450 PD7210 GTM 5010
Text: GPIB-1014 User Manual March 1997 Edition Part Number 370945A-01 Copyright 1985, 1997 National Instruments Corporation. All Rights Reserved. National Instruments Corporate Headquarters 6504 Bridge Point Parkway Austin, TX 78730-5039 512 794-0100 Technical support phone: (512) 795-8248
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GPIB-1014
70945A-01
GPIB-1014
PD7210
Index-21
Index-23
IEEE Standard 1014-1987
NEC uPD7210
F1241
LS2521
HD68450
MC68450
GTM 5010
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IEEE Standard 1014-1987
Abstract: GPIB-1014 diack 5b HD68450 MC68450 PD7210 LS2521 GTM 5010 25ls2521 scr205
Text: GPIB-1014 User Manual March 1997 Edition Part Number 320030-01 Copyright 1985, 1997 National Instruments Corporation. All Rights Reserved. National Instruments Corporate Headquarters 6504 Bridge Point Parkway Austin, TX 78730-5039 512 794-0100 Technical support phone: (512) 795-8248
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GPIB-1014
GPIB-1014
PD7210
Index-21
Index-23
IEEE Standard 1014-1987
diack 5b
HD68450
MC68450
LS2521
GTM 5010
25ls2521
scr205
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intel 845 MOTHERBOARD pcb CIRCUIT diagram
Abstract: TRANSISTOR SMD MARKING CODE 52s WD61C12 KHN 13100 transistor SMD 352a smd transistor marking 352a ECG transistor replacement guide book free TRANSISTOR REPLACEMENT ECG 27mhz remote control receiver ic rx 2b circuit FO WD90C26A
Text: OAT ABO 0 K 1992 DEVICES Systems Logic Imaging Storage ~ WESTERN DIGITAL Copyright 1992 Western Digital Corporation All Rights Reserved Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital Corporation for its use; nor for any infringements of
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CA92718
intel 845 MOTHERBOARD pcb CIRCUIT diagram
TRANSISTOR SMD MARKING CODE 52s
WD61C12
KHN 13100
transistor SMD 352a
smd transistor marking 352a
ECG transistor replacement guide book free
TRANSISTOR REPLACEMENT ECG
27mhz remote control receiver ic rx 2b circuit FO
WD90C26A
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EL640.480.aa1
Abstract: EL640.480 ad4 486dx schematic LCD 640X200 OPTREX el640.480 c3 LD4 SMD diode lcd seiko EPSON 486dx schematics compaq 486 motherboard diagram 89 33 35X SMD ELECTROLYTIC capacitor
Text: SPC8110F0A Local Bus LCD/CRT VGA Controller SPC8110F0A TECHNICAL MANUAL Issue Date: 98/01/27 Document No. X07G-Q-001-05 Copyright 1996, 1998 S-MOS Systems Inc. All rights reserved. This document, and any text derived, extracted or transmitted from it, is the sole property of S-MOS Systems Inc. and may not be used, copied,
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SPC8110F0A
X07G-Q-001-05
c-002-01
8110LD
8110LD4
8110LD5
8110LD6
8110LD7
8110LD0
EL640.480.aa1
EL640.480 ad4
486dx schematic
LCD 640X200 OPTREX
el640.480 c3
LD4 SMD diode
lcd seiko EPSON
486dx schematics
compaq 486 motherboard diagram
89 33 35X SMD ELECTROLYTIC capacitor
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74LS147
Abstract: 74ls147 pin diagram FUNCTIONAL APPLICATION OF 74LS148 74ls148 74LS147 equivalent motorola 74ls147 74ls748 SN54/74LS147 FAST AND LS TTL ls74
Text: SN54/74LS147 SN54/74LS148 SN54/74LS748 10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS The SN54 / 74LS147 and the SN54/ 74LS148 are Priority Encoders. They provide priority decoding of the inputs to ensure that only the highest order data line is encoded. Both devices have data inputs and outputs which are
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SN54/74LS147
SN54/74LS148
SN54/74LS748
10-LINE-TO-4-LINE
74LS147
74LS148
LS147
LS148
74ls147 pin diagram
FUNCTIONAL APPLICATION OF 74LS148
74LS147 equivalent
motorola 74ls147
74ls748
SN54/74LS147
FAST AND LS TTL
ls74
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74LS147
Abstract: 74ls147 pin diagram 74ls748 SN54/74LS147,SN54/74LS148 74LS148 motorola 74ls147 PIN 74LS147 74ls147 datasheet 74LS147 equivalent LS148
Text: SN54/74LS147 SN54/74LS148 SN54/74LS748 10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS The SN54 / 74LS147 and the SN54 / 74LS148 are Priority Encoders. They provide priority decoding of the inputs to ensure that only the highest order data line is encoded. Both devices have data inputs and outputs which are
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SN54/74LS147
SN54/74LS148
SN54/74LS748
10-LINE-TO-4-LINE
74LS147
74LS148
LS147
LS148
LS148)
LS748)
74ls147 pin diagram
74ls748
SN54/74LS147,SN54/74LS148
motorola 74ls147
PIN 74LS147
74ls147 datasheet
74LS147 equivalent
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74ls74a
Abstract: 751A-02
Text: SN54/74LS74A DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS74A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce high speed D-type flip-flops. Each flip-flop has individual clear and set inputs, and also complementary Q and Q outputs.
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SN54/74LS74A
74LS74A
751A-02
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74LS74A
Abstract: 751A-02
Text: SN54/74LS74A DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS74A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce high speed D-type flip-flops. Each flip-flop has individual clear and set inputs, and also complementary Q and Q outputs.
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SN54/74LS74A
74LS74A
751A-02
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74ls82
Abstract: 74245 BIDIRECTIONAL BUFFER IC 74ls150 ph 4531 diode 4583 dual schmitt trigger ic D flip flop 7474 74245 BUFFER IC ic 7483 BCD adder data sheet ic 74139 Quad 2 input nand gate cd 4093
Text: General Features The SCxD4 series of high perform ance CM O S gate arrays offers the user the ability to realise custom ised VLSI inte grated circuits featuring the speed perform ance previously obtainable only with bipo lar tech nolog ies whilst retaining all
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74LS82
Abstract: 74245 BIDIRECTIONAL BUFFER IC ic 4583 schmitt trigger core bit excess 3 adder using IC 7483 advantages for ic 7473 4 BIT COUNTER 74669 la 4508 ic schematic diagram XF107 74295 random number generator by using ic 4011 and 4017
Text: General Features The SCxD4 series of high performance CMOS gate arrays offers the user the ability to realise customised VLSI inte grated circuits featuring the speed performance previously obtainable only with bipolar technologies whilst retaining all the advantages of CMOS technology; low power consum p
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DM856
Abstract: SDM857KG SDM856JG SDM856 ic57 mpc8d S0M857 dig voltmeter SDM857 KG SDM857JG
Text: SDM856 SDM857 B U R R - B R O W N HYBRID DATA ACQUISITION SYSTEM FEATU RES DESCRIPTION The SDM856 and SDM857 are complete data acquisition systems contained in a miniature 2.2" x 1.7" x 0.22" ceramic package. These systems offer all the functions available in large modular data
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SDM856
SDM857
12-BIT,
S0M857)
S0M857
70kHz
10-Bit
32kHz
12-Bit
29kHz
DM856
SDM857KG
SDM856JG
ic57
mpc8d
dig voltmeter
SDM857 KG
SDM857JG
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Untitled
Abstract: No abstract text available
Text: SN5474, SN54LS74A, SN54S74, SN7474, SN74LS74A, SN74S74 DUAL D TYPE POSITIVE-EDGE-TRIGGERED FLIP FLOPS WITH PRESET AND CLEAR D E C E M B E R 1983 - R E V IS E D M A R C H 19B8 Package Options Include Plastic "Sm all Outline" Packages, Ceramic Chip Carriers
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SN5474,
SN54LS74A,
SN54S74,
SN7474,
SN74LS74A,
SN74S74
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sm 6136 b
Abstract: 3052v 15v
Text: MN5295 MN5296 17 /iSec, 16-Bit EXTENDED TEMPERATURE A/D CONVERTERS [U wmm MICRO NETWORKS DESCRIPTION FEATURES High re solution, high speed, sm all package and the a b ility to operate over extended tem p e ra tu re s including -5 5 ° C to + 125°C are brought to g e th e r in the MN5295 and MN5296.
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MN5295
MN5296
16-Bit
MN5296.
16-bit,
17/xsec
14-bit
MN5296
sm 6136 b
3052v 15v
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pin diagram and block diagram of 74ls74
Abstract: 74LS74 pinout 74LS74 SPECIFICATIONS 74LS74 PIN NUMBER DIAGRAM 74LS123 74ls74 flip-flop 74LS123 application circuits MN374H/Q2N3053 SHC76 ADC71
Text: MN374 y _ HIGH-SPEED HIGH-RESOLUTION TRACK-HOLD AMPLIFIER MICRO NETWORKS DESCRIPTION FEATURES • 4nsec M ax A cq uisition T im e 20V S tep to ± 0 .0 0 3 % • C o m p a tib le w ith All DIP P ackaged 14-16 Bit A /D ’s • 4 0 0 p s e c A p e rtu re Jitter
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MN374
400psec
14-Pin
SHC76
MIL-H-38534
MIL-STD-1772
MN374
43kHz
74LS123
50nsec-wide
pin diagram and block diagram of 74ls74
74LS74 pinout
74LS74 SPECIFICATIONS
74LS74 PIN NUMBER DIAGRAM
74ls74 flip-flop
74LS123 application circuits
MN374H/Q2N3053
SHC76
ADC71
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74LS74 PINOUT
Abstract: 74LS123A ADC71
Text: MN374 111 n HIGH-SPEED HIGH-RESOLUTION TRACK-HOLD AMPLIFIER m m l M IC R O N ETW O R K S DESCRIPTION FEATURES • 4^sec M ax A cq uisition T im e 20V S tep to + 0 .0 0 3 % • C o m p a tib le w ith All DIP P ackaged 14-16 Bit A /D ’s • 4 0 0 p s e c A p e rtu re Jitter
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MN374
14-Pln
MN374
74LS123
50nsec-w
43kHz
MN5295/
74LS74.
74LS74 PINOUT
74LS123A
ADC71
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74LS147
Abstract: 74LS148 PIN 74LS147
Text: M MOTOROLA D ESCRIPTIO N — The S N 5 4 L S /7 4 L S 147 and th e S N 54 L S /7 4 L S 148 SN54LS/74LS147 SN54LS/74LS148 SN54LS/74LS748 are Priority Encoders. They provide prio rity decoding of the inputs to ensure th a t only th e highest order data line is encoded. Both devices
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LS147
LS148
54LS74LS143
LS148)
LS748)
74LS147
74LS148
PIN 74LS147
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74LS147
Abstract: 74LS148 74ls748 LS748 PIN 74LS147 LS148 ttl 74ls147 LS 74LS147 6200S ttl 74ls148
Text: <8 > MOTOROLA SN54/74LS147 SN54/74LS148 SN54/74LS748 10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS The S N 54/74LS 147 and the S N 54/74LS 148 are Priority Encoders. They provide priority decoding of the inputs to ensure that only the highest order
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10-LINE-TO-4-LINE
54/74LS
LS147
LS148
SN54/74LS148
SN54/74LS748
LS148)
LS748)
74LS147
74LS148
74ls748
LS748
PIN 74LS147
ttl 74ls147
LS 74LS147
6200S
ttl 74ls148
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LS748
Abstract: 74LS147 74LS148 74lS748
Text: g MOTOROLA SN54/74LS147 SN54/74LS148 SN54/74LS748 10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS The S N 54/74LS 147 and the SN 54/74LS 148 are Priority Encoders. They provide priority decoding of the inputs to ensure that only the highest order
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10-LINE-TO-4-LINE
54/74LS
LS147
LS148
SN54/74LS148
SN54/74LS748
LS148)
LS748)
LS748
74LS147
74LS148
74lS748
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Untitled
Abstract: No abstract text available
Text: GD54/74LS74A DUAL D-TYPE POSITIVE EDGE-TRIGGERD FLIP-FLOPS WITH PRESET AND CLEAR Description This device contains two independent D-type positive edge triggered flip-flops. A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the
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GD54/74LS74A
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Untitled
Abstract: No abstract text available
Text: GD54/74LS74A DUAL D-TYPE POSITIVE EDGE-TRIGGERD FLIP-FLOPS W ITH PRESET AND CLEAR Description Pin Configuration This device contains two independent D-type positive edge triggered flip-flops. A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the
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GD54/74LS74A
DGGU21S
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74LS74A
Abstract: 54LS 74LS
Text: GD54/74LS74A DUAL D-TYPE POS.T.VE EDGE-TRIGGED FLIP-FLOPS Description Pin Configuration This device contains tw o ind epen den t D -typ e positive ed g e triggered flip-flops. A low level at the p reset or clear inputs sets or resets the outputs regardless of the levels of the
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GD54/74LS74A
configurat25Â
74LS74A
54LS
74LS
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74LS74A
Abstract: No abstract text available
Text: <g> MOTOROLA SN54/74LS74A DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP The S N 54/74LS 74A dual edge-triggered flip-flop utilizes Schottky TTL cir cuitry to produce high speed D-type flip-flops. Each flip-flop has individual clear and set inputs, and also com plementary Q and Q outputs.
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SN54/74LS74A
54/74LS
74LS74A
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