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    RM7000C

    Abstract: RM7000 600MHz RM7000 GT-6424 IEEE754
    Text: RM7000C Preliminary 64-Bit MIPS RISC Microprocessor with Integrated L2 Cache FEATURES 1600 Mbyte per-second peak throughput • 200 MHz max. freq., HSTL multiplexed address/data bus SysAD200 • Supports two outstanding reads with out-of-order return High-performance floating-point unit


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    PDF RM7000C 64-Bit SysAD200) IEEE754 32bit RM7000C RM7000 600MHz RM7000 GT-6424