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    STP1021A Search Results

    STP1021A Datasheets (3)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    STP1021A Sun Microelectronics SuperSPARC-II, SPARC v8 32-Bit Superscalar Microprocessor Scan PDF
    STP1021APGA-75 Sun Microelectronics SuperSPARC-II, SPARC v8 32-Bit Superscalar Microprocessor Scan PDF
    STP1021APGA-85 Sun Microelectronics SuperSPARC-II, SPARC v8 32-Bit Superscalar Microprocessor Scan PDF

    STP1021A Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Supersparc

    Abstract: IEEE754 STP1021A
    Text: STP1021A July 1997 SuperSPARC -II DATA SHEET SPARC v8 32-Bit Superscalar Microprocessor DESCRIPTION The STP1021A is a new member of the SuperSPARC-II family of microprocessor products. Like its predecessors STP1020N, STP1020 and STP1021 this new part is fully SPARC Version 8 compliant and is completely upward compatible with the earlier SPARC Version 7 implementations running over 9,400 SPARC applications and development


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    PDF STP1021A 32-Bit STP1021A STP1020N, STP1020 STP1021) instructionta32 addr18 data50 Supersparc IEEE754

    free mbus master

    Abstract: SuperSPARC VOLTAGE REGULATOR 78 IEEE754 SS20 STP1021A STP5011D STP5011DMBUS75 M-BUS mbus controllers
    Text: STP5011D July 1997 SuperSPARC -II MBus Modules DATA SHEET 75/85 MHz SuperSPARC-II + 1 MB E-Cache DESCRIPTION The STP5011D is the MBus module incorporating the latest SuperSPARC-II microprocessor. This module provides a CPU sub-system with the high performance superscalar SuperSPARC-II microprocessor STP1021A


    Original
    PDF STP5011D STP5011D STP1021A) STP1091) IEEE754 KByte021A. STP5011DMBUS-75 free mbus master SuperSPARC VOLTAGE REGULATOR 78 SS20 STP1021A STP5011DMBUS75 M-BUS mbus controllers

    TMx390

    Abstract: SuperSPARC STP1020 STP1021A MAD19 STP1091 ADDR02 Mbus master 250 slave circuit stp1090 imad-26
    Text: STP1091.frm Page 97 Monday, August 25, 1997 3:08 PM STP1091 July 1997 Multi-Cache Controller DATA SHEET Integrated Cache Controller for SuperSPARC DESCRIPTION The STP1091 is a high-performance external cache controller for the STP1020 SuperSPARC and STP1021 (SuperSPARC-II) microprocessors. It is used when a large secondary cache or an interface to a non-MBus system is required.


    Original
    PDF STP1091 STP1091 STP1020 STP1021 33x8k TMx390 SuperSPARC STP1020 STP1021A MAD19 ADDR02 Mbus master 250 slave circuit stp1090 imad-26

    supersparc

    Abstract: HY 1021A Sun STP1021 3AR3 cap 220 htz ADA33
    Text: [ f ^ T l r í A C K j S un M i c r o e l e c t r o n i c s July 1997 SuperSPARC“-ll DATA SHEET SPARC v8 32-Bit Superscalar Microprocessor D e s c r ip t io n The STP1021A is a new m em ber of the Su p erSPA R C T I fam ily o f m icroprocessor products. L ik e its predeces­


    OCR Scan
    PDF STP1021A STP1020N, STP1020 STP1021) cl277 data12 STP1021APGA-85 STP1021APGA-75 supersparc HY 1021A Sun STP1021 3AR3 cap 220 htz ADA33

    supersparc

    Abstract: Sun STP1021
    Text: S un M icro electro nics July 1997 SuperSPARCT“-ll DATA SHEET SPARC v8 32-Bit Superscalar Microprocessor D e s c r ip t io n The STP1021A is a new member of the SuperSPARC-II family of microprocessor products. Like its predeces­ sors STP1020N, STP1020 and STP1021 this new part is fully SPARC Version 8 compliant and is completely


    OCR Scan
    PDF STP1021A STP1020N, STP1020 STP1021) 32-Bit STP1021APGA-85 STP1021APGA-75 STP1021A supersparc Sun STP1021

    Untitled

    Abstract: No abstract text available
    Text: STP1021A S un M ic r o e l e c t r o n ic s J u ly 1997 SuperSPARC -ll DATA SHEET SPARC v8 32-Bit Superscalar Microprocessor D e s c r ip t io n The STP1021A is a new m em ber of the SuperSPARC-II fam ily of m icroprocessor products. Like its predeces­


    OCR Scan
    PDF STP1021A 32-Bit STP1021A STP1020N, STP1020 STP1021) data32 data49 data31

    lcd cross reference

    Abstract: SME2411BGA SuperSPARC 805-0086-02 PMC cross reference STP2003QFP ATM622-S STP3010 STP2014QFP STP2024QFP
    Text: S un M icroelectronics July 1997 Data Sheets listed by Product Name Cross Reference List Advanced PCI Bridge SME2411BGA ATM622-S SAR SME4050BGA 802-7894-02 Color LCD Controller STP3031 STP3031 Crossbar Switch XB1 STP2230SOP 802-7955-02 Dual System Controller


    OCR Scan
    PDF ATM622-S 85/110MHz UltraSPARC-1167 UltraSPARC-11 UltraSPARC-ll/300 Buffer-50 STP1030A STP5111A-200 STP5110A-167 lcd cross reference SME2411BGA SuperSPARC 805-0086-02 PMC cross reference STP2003QFP STP3010 STP2014QFP STP2024QFP

    SuperSPARC

    Abstract: Mbus master 250 slave circuit tmx390 STP1091-60
    Text: S un M icroelectronics July 1997 Multi-Cache Controller DATA SHEET Integrated Cache Controller for SuperSPARC D e s c r ip t io n The STP1091 is a high-performance external cache controller for the STP1020 SuperSPARC and STP1021 (SuperSPARC-II) microprocessors. It is used when a large secondary cache or an interface to a non-MBus sys­


    OCR Scan
    PDF STP1091 STP1020 STP1021 33x8k STP1091PGA-75 STP1091PGA-90 STP1020HS STP1091 SuperSPARC Mbus master 250 slave circuit tmx390 STP1091-60

    Untitled

    Abstract: No abstract text available
    Text: STP1091 S un M ic r o e l e c t r o n ic s J u ly 1997 Multi-Cache Controller DATA SHEET Integrated Cache Controller for SuperSPARC D e s c r ip t io n The STP1091 is a high-perform ance external cache controller for the STP1020 SuperSPARC and STP1021


    OCR Scan
    PDF STP1091 STP1091 STP1020 STP1021 33x8k 1091PG STP1020H

    SuperSPARC

    Abstract: STP1020 mbus sparc IEEE754 STP1021A instruction set Sun SPARC T4 instruction set Sun SPARC T6
    Text: ST P 1021A S un M icro electro nics J u ly 1997 SuperSPARC -ll DATA SHEET SPARC v8 32-Bit Superscalar Microprocessor D e s c r ip t io n T h e ST P 1021A is a n e w m em b er o f the SuperSP A R C -II fam ily o f m icro p ro cesso r prod u cts. L ik e its p red eces­


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    PDF 32-Bit STP1021A STP1020N, STP1020 STP1021) data50 data32 data49 data31 SuperSPARC mbus sparc IEEE754 instruction set Sun SPARC T4 instruction set Sun SPARC T6

    supersparc

    Abstract: STP2003QFP STP3010PGA 805-0086-02 lcd cross reference STP2013 PMC cross reference STP3010 ATM622-S STP2024QFP
    Text: S un M icroelectronics July 1997 Data Sheets listed by Marketing Part Cross Reference List M a r k e t in g P a r t 501-4126 Fast Frame Buffer 3D 802-7509-02 501-4127 Fast Frame Buffer (2D) 802-7509-02 SME1040BGA UltraSPARC-ll/ 300 MHz 805-0086-02 SME2411BGFA


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    PDF SME1040BGA SME2411BGFA SME4050BGA STP1012PGA-85, STP1021APGA STP1030A STP1031 LGA-250 STP1080A STP1081 supersparc STP2003QFP STP3010PGA 805-0086-02 lcd cross reference STP2013 PMC cross reference STP3010 ATM622-S STP2024QFP

    E5OU

    Abstract: Lr d14 instruction set Sun SPARC T4 instruction set Sun SPARC T2 STP1021A
    Text: Preliminary SPARC Technology Business STP1021 J u n e 1995 SuperSPARC II DATA SHEET Highly Integrated 3 2-Bit RISC Microprocessor D e s c r ip t io n The STP1021 is a new member of the SuperSPARC II family of microprocessor products. Like its predecessors


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    PDF STP1021 STP1021 STP1020N STP1020) E5OU Lr d14 instruction set Sun SPARC T4 instruction set Sun SPARC T2 STP1021A

    m-bus c#

    Abstract: No abstract text available
    Text: S T P 5011D S un M ic r o e le c t r o n ic s J u ly 1997 SuperSPARC -ll MBus Modules DATA SHEET 75/85 MHz SuperSPARC-II + 1 MB E-Cache D e s c r ip t io n The STP5011D is the M Bus m odule incorporating the latest SuperSFARC-II microprocessor. This m odule pro­


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    PDF 5011D STP5011D STP1021A) STP1091) IEEE754 STP501 STP5011D m-bus c#

    Untitled

    Abstract: No abstract text available
    Text: STP5011D S un M ic r o e l e c t r o n ic s J u ly 1997 SuperSPARC”-ll MBus Modules DATA SHEET 75/85 MHz SuperSPARC-II + 1 MB E-Cache D e s c r ip t io n The STP5011D is the M Bus m odule incorporating the latest SuperSPARC-II microprocessor. This m odule pro­


    OCR Scan
    PDF STP5011D STP5011D STP1021A) STP1091) IEEE754 5011DMBUS-75

    6253A

    Abstract: supersparc
    Text: S un M icroelectronics July 1997 SuperSPARCT"-ll MBus Modules DATA SHEET 75/85 MHz SuperSPARC-II + 1 MB E-Cache D e s c r ip t io n The STP5011D is the M Bus m odule incorporating the latest SuperSPARC-II microprocessor. This m odule pro­ vides a CPU sub-system with the high perform ance superscalar SuperSPARC-II microprocessor STP1021 A


    OCR Scan
    PDF STP5011D STP1021 STP1091) IEEE754 STP1021A STP5011D 6253A supersparc

    instruction set Sun SPARC T6

    Abstract: Cache Controller SPARC Sun STP1021 Sun Sparc II
    Text: Pre lim i n a n 4^ Sun STP1021 October 1994 SuperSPARC II DMA SHEET Highly Integrated 32-Bit RISC Microprocessor D esc r ip t io n The STP1021 is a new member of the SuperSPARC II family of microprocessor products. Like its predecessors STP1020N and STP1020 this new part is fully SPARC version 8 compliant and is completely upward compatible


    OCR Scan
    PDF STP1021 32-Bit STP1021 STP1020N STP1020) STP1021is instruction set Sun SPARC T6 Cache Controller SPARC Sun STP1021 Sun Sparc II

    TRANSISTOR R 40 AH-16

    Abstract: TEA 1091 TRANSISTOR AH-16 sparc v8 AD04M l xd 402 mf xd 402 mf STP1091-60
    Text: Prelim inary SPARC Technology Business DATA SHEET D STP1091 _ February 1995 M u lti- C a c h e C ontroller Integrated Cache Controller for SuperSPARC escription The STP1091 is a high-performance external cache controller for the STP1020 SuperSPARC and STP1021


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    PDF STP1091 STP1091 STP1020 STP1021 33x8k TRANSISTOR R 40 AH-16 TEA 1091 TRANSISTOR AH-16 sparc v8 AD04M l xd 402 mf xd 402 mf STP1091-60