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TAIYO YUDEN JWK105BJ104MP-F CAP CER 0.1UF 6.3V X5R 0204
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	JWK105BJ104MP-F	Reel			10,000	1 - 10 - 100 - 1000 - 10000 $0.01897	Buy Now
Avnet Americas	JWK105BJ104MP-F	Reel			10,000	1 - 10 - 100 - 1000 - 10000 $0.01533	Buy Now
Mouser Electronics	JWK105BJ104MP-F		9,990			1 $0.11 10 $0.072 100 $0.036 1000 $0.023 10000 $0.018	Buy Now
Onlinecomponents.com	JWK105BJ104MP-F					1 $0 10 $0 100 $0 1000 $0 10000 $0	Buy Now
TAIYO YUDEN JWK105 BJ104MP-F Multilayer Ceramic Capacitor, 0.1 uF, 6.3 V, ï¿½ 20%, X5R, 0204 [0510 Metric] (Alt: CEJWK105BJ104MP-F)
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Avnet Abacus	JWK105 BJ104MP-F			17 Weeks	10,000	1 - 10 - 100 - 1000 - 10000 -	Buy Now

JWK105BJ104MP Datasheets (1)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
JWK105BJ104MP-F		Taiyo Yuden	Capacitors - Ceramic Capacitors - CAP CER 0.1UF 6.3V X5R 0204		Original	PDF

JWK105BJ104MP Datasheets Context Search

Catalog Datasheet	MFG & Type	PDF	Document Tags
JWK105BJ104MP Abstract: No abstract text available Text: Multi Layer Ceramic Capacitor -Electrical Characteristics Data- 10YC09O RoHS compliance product ○JWK105BJ104MP 6.3V 0510 X5R 0.1uF +/-20% t=0.35mmMAX 6.3V 0204 X5R 0.1uF +/-20% t=0.014inchMAX JWK105BJ104MP DC Bias Char. 20 JWK105BJ104MP Capacitance Freq.	Original	PDF	10YC09O JWK105BJ104MP 35mmMAX 014inchMAX JWK105BJ104MP
Untitled Abstract: No abstract text available Text: TPS51206 SLUSAH1 – MAY 2011 www.ti.com 2-A Peak Sink/Source DDR Termination Regulator with VTTREF Buffered Reference For DDR2, DDR3 and DDR3L Check for Samples: TPS51206 FEATURES APPLICATIONS • • • 1 2 • • • • • • Supply Input Voltage: Supports 3.3-V Rail and	Original	PDF	TPS51206 10-mA 10-pin
Untitled Abstract: No abstract text available Text: TPS51206 www.ti.com SLUSAH1A – MAY 2011 – REVISED OCTOBER 2013 2-A Peak Sink/Source DDR Termination Regulator with VTTREF Buffered Reference For DDR2, DDR3 and DDR3L Check for Samples: TPS51206 FEATURES APPLICATIONS • • • 1 2 • • • • •	Original	PDF	TPS51206 10-mA
TPS51206 Abstract: No abstract text available Text: TPS51206 SLUSAH1 – MAY 2011 www.ti.com 2-A Peak Sink/Source DDR Termination Regulator with VTTREF Buffered Reference For DDR2, DDR3 and DDR3L Check for Samples: TPS51206 FEATURES APPLICATIONS • • • 1 2 • • • • • • Supply Input Voltage: Supports 3.3-V Rail and	Original	PDF	TPS51206 10-mA 10-pin TPS51206
LG124C104MAT2S1 Abstract: LQW15AN19HJ00 tosa flex cable design HFRD-49 JWK105BJ104MP-F 10G BERT TOSA ROsa BLM15GG471SN1D HFRD maxim HFRD-30 Text: Reference Design: HFRD-49.1 Rev 0; 8/10 Multirate, 1.0625Gbps to 10.3125Gbps, SFP+ LR Transceiver Maxim Integrated Products Multirate, 1.0625 to 10.3125Gbps, SFP+ LR Transceiver Table of Contents 1 2 3 4 5 6 7 8 9 Overview Reference-Design Details Performance Data	Original	PDF	HFRD-49 0625Gbps 3125Gbps, MAX3946 MAX3945 DS1878 LG124C104MAT2S1 LQW15AN19HJ00 tosa flex cable design JWK105BJ104MP-F 10G BERT TOSA ROsa BLM15GG471SN1D HFRD maxim HFRD-30
ddr3l pcb design guide Abstract: TPS51206-EVM TPS51206 jmk107bj106ma JWK105BJ104MP Text: TPS51206 SLUSAH1 – MAY 2011 www.ti.com 2-A Peak Sink/Source DDR Termination Regulator with VTTREF Buffered Reference For DDR2, DDR3 and DDR3L Check for Samples: TPS51206 FEATURES APPLICATIONS • • • 1 2 • • • • • • Supply Input Voltage: Supports 3.3-V Rail and	Original	PDF	TPS51206 10-mA 10-pin ddr3l pcb design guide TPS51206-EVM TPS51206 jmk107bj106ma JWK105BJ104MP
Untitled Abstract: No abstract text available Text: TPS51206 SLUSAH1 – MAY 2011 www.ti.com 2-A Peak Sink/Source DDR Termination Regulator with VTTREF Buffered Reference For DDR2, DDR3 and DDR3L Check for Samples: TPS51206 FEATURES APPLICATIONS • • • 1 2 • • • • • • Supply Input Voltage: Supports 3.3-V Rail and	Original	PDF	TPS51206 10-mA 10-pin
DDR3 pcb layout guidelines Abstract: No abstract text available Text: TPS51206 SLUSAH1 – MAY 2011 www.ti.com 2-A Peak Sink/Source DDR Termination Regulator with VTTREF Buffered Reference For DDR2, DDR3 and DDR3L Check for Samples: TPS51206 FEATURES APPLICATIONS • • • 1 2 • • • • • • Supply Input Voltage: Supports 3.3-V Rail and	Original	PDF	TPS51206 10-mA 10-pin DDR3 pcb layout guidelines
Untitled Abstract: No abstract text available Text: TPS51206 SLUSAH1 – MAY 2011 www.ti.com 2-A Peak Sink/Source DDR Termination Regulator with VTTREF Buffered Reference For DDR2, DDR3 and DDR3L Check for Samples: TPS51206 FEATURES APPLICATIONS • • • 1 2 • • • • • • Supply Input Voltage: Supports 3.3-V Rail and	Original	PDF	TPS51206 10-mA 10-pin