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Infineon Technologies AG CY7C1911UV18-300BZC IC SRAM 18MBIT PARALLEL 165FBGA
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DigiKey	CY7C1911UV18-300BZC	Bag			1	1 $53.47 10 $53.47 100 $53.47 1000 $53.47 10000 $53.47	Buy Now
Infineon Technologies AG CY7C1911JV18-300BZC IC SRAM 18MBIT PARALLEL 165FBGA
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DigiKey	CY7C1911JV18-300BZC	Tray			119	1 - 10 - 100 - 1000 $33.86311 10000 $33.86311	Buy Now
Rochester Electronics LLC CY7C1911JV18-300BZC IC SRAM 18MBIT PARALLEL 165FBGA
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DigiKey	CY7C1911JV18-300BZC	Tray			7	1 - 10 $43.66 100 $43.66 1000 $43.66 10000 $43.66	Buy Now
Infineon Technologies AG CY7C1911KV18-300BZC IC SRAM 18MBIT PARALLEL 165FBGA
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DigiKey	CY7C1911KV18-300BZC	Tray				1 - 10 - 100 - 1000 - 10000 -	Buy Now
Rochester Electronics LLC CY7C1911KV18-300BZC IC SRAM 18MBIT PARALLEL 165FBGA
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DigiKey	CY7C1911KV18-300BZC	Bulk			10	1 - 10 $32.25 100 $32.25 1000 $32.25 10000 $32.25	Buy Now

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CY7C191 Datasheets (94)

Part	Manufacturer	Description	Datasheet Type	PDF
CY7C191	Cypress Semiconductor	64K x 4 Static RAM with Separate I/O	Original	PDF
CY7C1910BV18	Cypress Semiconductor	18-Mbit QDR-II SRAM 2-Word Burst Architecture	Original	PDF
CY7C1910BV18-167BZC	Cypress Semiconductor	18-Mbit QDR-II SRAM 2-Word Burst Architecture	Original	PDF
CY7C1910BV18-167BZXC	Cypress Semiconductor	18-Mbit QDR-II SRAM 2-Word Burst Architecture	Original	PDF
CY7C1910BV18-200BZC	Cypress Semiconductor	18-Mbit QDR-II SRAM 2-Word Burst Architecture	Original	PDF
CY7C1910BV18-250BZC	Cypress Semiconductor	18-Mbit QDR-II SRAM 2-Word Burst Architecture	Original	PDF
CY7C1910CV18	Cypress Semiconductor	18-Mbit QDR-II SRAM 2-Word Burst Architecture	Original	PDF
CY7C191-12DC	Cypress Semiconductor	65,536 x 4 Static R/W RAM Separate I/O	Scan	PDF
CY7C191-12LC	Cypress Semiconductor	65,536 x 4 Static R/W RAM Separate I/O	Scan	PDF
CY7C191-12PC	Cypress Semiconductor	64K x 4 Static RAM with Separate I/O	Original	PDF
CY7C191-12PC	Cypress Semiconductor	64K x 4 Static RAM with Separate I/O	Scan	PDF
CY7C191-12PC	Cypress Semiconductor	65,536 x 4 Static R/W RAM Separate I/O	Scan	PDF
CY7C191-12PC	Cypress Semiconductor	64K x 4 Static RAM with Separate I/O	Scan	PDF
CY7C191-12VC	Cypress Semiconductor	64K x 4 Static RAM with Separate I/O	Original	PDF

CY7C191-12VC	Cypress Semiconductor	64K x 4 Static RAM with Separate I/O	Scan	PDF
CY7C191-12VC	Cypress Semiconductor	65,536 x 4 Static R/W RAM Separate I/O	Scan	PDF
CY7C191-12VC	Cypress Semiconductor	64K x 4 Static RAM with Separate I/O	Scan	PDF
CY7C191-15DC	Cypress Semiconductor	65,536 x 4 Static R/W RAM Separate I/O	Scan	PDF
CY7C191-15DMB	Cypress Semiconductor	65,536 x 4 Static R/W RAM Separate I/O	Scan	PDF
CY7C191-15KMB	Cypress Semiconductor	65,536 x 4 Static R/W RAM Separate I/O	Scan	PDF

CY7C191 Datasheets Context Search

Catalog Datasheet	MFG & Type	PDF	Document Tags
c1918 Abstract: C1915 CY7C192-25PC 7C192-12 7C192-15 C191 CY7C191 CY7C192 C1914 Text: 1CY 7C19 2 CY7C191 CY7C192 64K x 4 Static RAM with Separate I/O Features Easy memory expansion is provided by active LOW chip enable CE and three-state drivers. They have an automatic power-down feature, reducing the power consumption by 75% when deselected.	Original	PDF	CY7C191 CY7C192 7C191) c1918 C1915 CY7C192-25PC 7C192-12 7C192-15 C191 CY7C191 CY7C192 C1914
CY7C1316BV18 Abstract: CY7C1318BV18 CY7C1320BV18 CY7C1916BV18 Text: CY7C1316BV18 CY7C1916BV18 CY7C1318BV18 CY7C1320BV18 PRELIMINARY 18-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 • 250-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency	Original	PDF	CY7C1316BV18 CY7C1916BV18 CY7C1318BV18 CY7C1320BV18 18-Mbit 250-MHz CY7C1316BV18 CY7C1318BV18 CY7C1320BV18 CY7C1916BV18
CY7C1311CV18 Abstract: CY7C1313CV18 CY7C1315CV18 CY7C1911CV18 Text: CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz clock for high bandwidth ■	Original	PDF	CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 18-Mbit CY7C1311CV18 CY7C1313CV18 CY7C1311CV18 CY7C1313CV18 CY7C1315CV18 CY7C1911CV18
CY7C1310BV18 Abstract: CY7C1312BV18 CY7C1314BV18 CY7C1910BV18 Text: CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit QDR -II SRAM 2 Word Burst Architecture Features Functional Description Separate Independent read and write data ports ❐ Supports concurrent transactions • 250 MHz clock for high bandwidth ■ 2 Word Burst on all accesses	Original	PDF	CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit CY7C1310BV18, CY7C1910BV18, CY7C1312BV18, CY7C1314BV18 CY7C1310BV18 CY7C1312BV18 CY7C1910BV18
CY7C1311BV18 Abstract: CY7C1313BV18 CY7C1315BV18 CY7C1911BV18 Text: CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300-MHz clock for high bandwidth	Original	PDF	CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 18-Mbit 300-MHz CY7C1311BV18 CY7C1313BV18 CY7C1315BV18 CY7C1911BV18
Untitled Abstract: No abstract text available Text: CY7C1310KV18, CY7C1910KV18 CY7C1312KV18, CY7C1314KV18 18-Mbit QDR II SRAM Two-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1310KV18 – 2 M x 8 ■ 333 MHz clock for high bandwidth	Original	PDF	18-Mbit CY7C1310KV18, CY7C1910KV18 CY7C1312KV18, CY7C1314KV18 CY7C1310KV18 CY7C1910KV18 CY7C1312KV18
Untitled Abstract: No abstract text available Text: CY7C1316BV18 CY7C1916BV18 CY7C1318BV18 CY7C1320BV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency	Original	PDF	CY7C1316BV18 CY7C1916BV18 CY7C1318BV18 CY7C1320BV18 18-Mbit 300-MHz
Untitled Abstract: No abstract text available Text: CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit QDR-II SRAM 2-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 250-MHz clock for high bandwidth	Original	PDF	CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit 250-MHz
Untitled Abstract: No abstract text available Text: CY7C1311CV18 CY7C1911CV18 CY7C1313CV18 CY7C1315CV18 PRELIMINARY 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports • QDR-II operates with 1.5 cycle read latency when the DLL is enabled	Original	PDF	CY7C1311CV18 CY7C1911CV18 CY7C1313CV18 CY7C1315CV18 18-Mbit 300-MHz 600MHz)
Untitled Abstract: No abstract text available Text: CY7C1317BV18 CY7C1319BV18 CY7C1321BV18 PRELIMINARY 18-Mbit DDR-II SRAM 4-Word Burst Architecture Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 The CY7C1317BV18, CY7C1917BV18, CY7C1319BV18, and CY7C1321BV18 are 1.8V Synchronous Pipelined SRAM	Original	PDF	CY7C1317BV18 CY7C1319BV18 CY7C1321BV18 18-Mbit 300-MHz 600MHz) CY7C1917BV18 BB165E
Untitled Abstract: No abstract text available Text: CY7C1310KV18, CY7C1910KV18 CY7C1312KV18, CY7C1314KV18 18-Mbit QDR II SRAM Two-Word Burst Architecture 18-Mbit QDR® II SRAM Two-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions	Original	PDF	CY7C1310KV18, CY7C1910KV18 CY7C1312KV18, CY7C1314KV18 18-Mbit CY7C1310KV18 CY7C1312KV18
CY7C1320KV18 Abstract: No abstract text available Text:  CY7C1316KV18, CY7C1916KV18 CY7C1318KV18, CY7C1320KV18 18-Mbit DDR II SRAM Two-Word Burst Architecture 18-Mbit DDR II SRAM Two-Word Burst Architecture Features Configurations • 18-Mbit density 2 M x 8, 2 M × 9, 1 M × 18, 512 K × 36 CY7C1316KV18 – 2 M × 8	Original	PDF	CY7C1316KV18, CY7C1916KV18 CY7C1318KV18, CY7C1320KV18 18-Mbit CY7C1316KV18 333-MHz CY7C1320KV18
Untitled Abstract: No abstract text available Text: CY7C1310JV18, CY7C1910JV18 CY7C1312JV18, CY7C1314JV18 18 Mbit QDR -II SRAM 2-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1310JV18 – 2M x 8 CY7C1910JV18 – 2M x 9	Original	PDF	CY7C1310JV18, CY7C1910JV18 CY7C1312JV18, CY7C1314JV18 CY7C1310JV18 CY7C1312JV18
Untitled Abstract: No abstract text available Text: CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 PRELIMINARY 18-Mbit QDR-II SRAM 2-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 250-MHz clock for high bandwidth	Original	PDF	CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 18-Mbit 250-MHz

93191 Abstract: sumitomo 6300h mold compound CY7C191 CY7C192 CY7C194 CY7C195 CY7C196 CY7C197 CY7C198 CY7C199 Text: PAGE 1 CYPRESS SEMICONDUCTOR Qualification Report July, 1994, QTP#93192/93191, Version 2.4 256K SRAM, RAM 2.1 SHRINK MARKETING PART NUMBER DEVICE DESCRIPTION CY7C191 64K x 4 Separate IO with transparent write CY7C192 64K x 4 Separate IO without transparent write	Original	PDF	CY7C191 CY7C192 CY7C194 CY7C195 CY7C196 CY7C197 CY7C198 CY7C199 15psig) 93191 sumitomo 6300h mold compound CY7C191 CY7C192 CY7C194 CY7C195 CY7C196 CY7C197 CY7C198 CY7C199
CY7C1311BV18 Abstract: CY7C1313BV18 CY7C1315BV18 CY7C1911BV18 Text: CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300-MHz clock for high bandwidth	Original	PDF	CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 18-Mbit 300-MHz CY7C1311BV18 CY7C1313BV18 CY7C1315BV18 CY7C1911BV18
Untitled Abstract: No abstract text available Text: CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300-MHz clock for high bandwidth	Original	PDF	CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 18-Mbit 300-MHz 600MHz) SelecCY7C1911BV18 278-MHz
CY7C1316JV18 Abstract: CY7C1318JV18 CY7C1320JV18 CY7C1916JV18 Text: CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 ■ 300 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency	Original	PDF	CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18 18-Mbit CY7C1316JV18 CY7C1318JV18 CY7C1320JV18 CY7C1916JV18
7C192-12 Abstract: 7C192-15 7C192-20 A10C CY7C191 CY7C192 CY7C192-25PC Text: MbE D CYPRESS SEMICON DUC TOR B 250^fc,b2 OOQfc.1,42 3 E 3 C Y P CY7C191 CY7C192 CYPRESS SEMICONDUCTOR Features • Automatic power-down when deselected • Transparent write 7C19X • CMOS for optimum speed/power • H ighspeed — tM = 25 ns • Low active power	OCR Scan	PDF	CY7C191 CY7C192 7C19X) TheCY7C191 CY7C192 CY7C192-45VC CY7C192-45DMB CY7C192-45KMB CY7C192â 45LMB 7C192-12 7C192-15 7C192-20 A10C CY7C192-25PC
7C192-12 Abstract: 7C192-15 A10C CY7C191 CY7C192 CY7C192-25PC Text: CY7C191 CY7C192 ir CYPRESS 64K x 4 Static RAM with Separate I/O Features Functional Description • High speed T he CY7C191 and CY7C192 are high perform ance CM OS static RAM s orga nized as 65,536 x 4 bits with separate I/O. Easy m em ory expansion isprovided by ac	OCR Scan	PDF	CY7C191 CY7C192 CY7C191) CY7C192 38-00076-J tAW15! tADvI15! 7C192-12 7C192-15 A10C CY7C192-25PC
Untitled Abstract: No abstract text available Text: CY7C191 CY7C192 " ^ cÌ press SEMICONDUCTOR Features • Automatic power-down when deselected • Transparent write 7C191 • CMOS for optimum speed/power • High speed — ‘ a a = 2 5 ns • Low active power — 880 raW • Low standby power 65,536 x 4 Static R/W RAM	OCR Scan	PDF	CY7C191 CY7C192 7C191) 7C192
Untitled Abstract: No abstract text available Text: CY7C191 CY7C192 PRELIMINARY CYPRESS SEMICONDUCTOR Features Functional Description • High speed — 12 ns • Transparent write 7C191 • CMOS for optimum speed/power • Low active power — 880 mW • Low standby power — 220 mW • TTL-compatible inputs and outputs	OCR Scan	PDF	CY7C191 CY7C192 7C191) CY7C191 CY7C192 tADvl15^
Untitled Abstract: No abstract text available Text: CY7C191 CY7C192 b m - . C Y PR ESS r SEMICONDUCTOR Features • Automatic power-down when deselected • Transparent write 7C191 • CMOS for optimum speed/power • Highspeed — tAA = 25 ns • Low active power — 880 mW • Low standby power	OCR Scan	PDF	CY7C191 CY7C192 7C191) CY7C192â 35KMB 35LMB
7C192-12 Abstract: 7C192-15 A10C CY7C191 CY7C192 CY7C192-25PC Text: CY7C191 CY7C192 if CYPRESS 64K x 4 Static RAM with Separate I/O Features Functional Description • High speed — 12 ns • Transparent write CY7C191 • CMOS for optimum speed/power • Low active power T he CY7C191 and CY7C192 are highperform ance CM OS static RAM s orga	OCR Scan	PDF	CY7C191 CY7C192 CY7C191) CY7C192 CY7C192â 45LMB 28-Pin 38-00076-J tADvI15! 7C192-12 7C192-15 A10C CY7C192-25PC

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CY7C191 Search Results

CY7C191 Price and Stock

Infineon Technologies AG CY7C1911UV18-300BZC

Infineon Technologies AG CY7C1911JV18-300BZC

Rochester Electronics LLC CY7C1911JV18-300BZC

Infineon Technologies AG CY7C1911KV18-300BZC

Rochester Electronics LLC CY7C1911KV18-300BZC

CY7C191 Datasheets (94)

CY7C191 Datasheets Context Search

c1918

CY7C1316BV18

CY7C1311CV18

CY7C1310BV18

CY7C1311BV18

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Untitled

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Untitled

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CY7C1320KV18

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93191

CY7C1311BV18

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CY7C1316JV18

7C192-12

7C192-12

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7C192-12