CY27S03A
Abstract: 15JC10 CY7C190 cy7c9101 cy7c122 die VIC068A user guide
Text: Thermal Management and Component Reliability slope of the logarithmic plots is given by the activation energy of the failure mechanisms causing thermally activated wear out of the device see Figure 1 . One of the key variables determining the long-term reliability
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CY7C122
CY27S03A
15JC10
CY7C190
cy7c9101
cy7c122 die
VIC068A user guide
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CY7C9101
Abstract: CY7C510 CY7C190 cy7c189 G30-88 CY7c910 EA 9394 cy3341 CY6116 cy7c901
Text: fax id: 8511 Thermal Management Thermal Management and Component Reliability One of the key variables determining the long-term reliability of an integrated circuit is the junction temperature of the device during operation. Long-term reliability of the semiconductor chip degrades proportionally with increasing temperatures following an exponential function described by the
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Untitled
Abstract: No abstract text available
Text: CY7C183 CY7C184 CYPRESS SEMICONDUCTOR Features • Pin-programmable into directmapped or two-way set-associative format • CMOS for optimum speed/power • H ighspeed — 20 n s • Common I/O • Internal address latch • TTL-compatible inputs and outputs
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CY7C183
CY7C184
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Untitled
Abstract: No abstract text available
Text: PRELIM IN ARY CYPRESS SEMICONDUCTOR CY7C183 CY7C184 2 x 4096 x 16 Cache RAM Features • Pin programmable into direct mapped or two-way set associative format • CMOS for optimum speed/ power • High speed—25 ns • Common I/O • Internal address latch
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CY7C183
CY7C184
CY7C183
CY7C184
16-bit
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CY7C183
Abstract: CY7C184 CY7C184-25JC oec18 7C183
Text: CY7C183 CY7C184 CYPRESS SEMICONDUCTOR Features • Pin-programmable into directmapped or two-way set-associative format • CMOS for optimum speed/power • High speed — 20 ns • Common I/O • Internal address latch • TTL-compatible inputs and outputs
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CY7C183
CY7C184
CY7C184are
16-bit
CY7C184â
35LMB
CY7C184-25JC
oec18
7C183
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7C184
Abstract: No abstract text available
Text: CY7C183 CY7C184 CYPRESS SEMICONDUCTOR Features • Pin-programmable into directmapped or two-way set-associative format • CMOS for optimum speed/power • H ighspeed — 20 ns • Common I/O • Internal address latch • TTL-compatible inputs and outputs
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CY7C183
CY7C184
7C184
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40ebl
Abstract: No abstract text available
Text: Data Sheet January 1992 ATT7C183 ATT7C184 ^ A T fiT Microelectronics High-Speed CMOS SRAM 128 Kbit 2 x 4K x 16 or 8K x 16 Cache-Data Features • High-speed — 25 ns maximum access time Plug-compatible with Cypress CY7C183/184 ■ Direct map or two-way set associative
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ATT7C183
ATT7C184
CY7C183/184
48-pin,
ATT7C184
7C194
ATT7C183
52-Pin,
40ebl
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toshiba 32k*8 sram
Abstract: M5M23C100 M5M5265 seeq DQ2816A M5M23C400 MB832001 HITACHI 64k DRAM TC511000 KM41C464 TC51464
Text: FUNCTION GUIDE MEMORY ICs 3. CROSS REFERENCE GUIDE 3.1 DRAM Density 64 K X 1 256K X 1 X4 1M X X 4M X X 3.2 Mode Org. 1 4 1 4 Samsung Toshiba Hitachi Fujitsu NEC MSM3764 KM4164 Page Okl F. Page KM41C256 TC51256 Nibble KM41C257 TC51257 HM51256 S. Column KM41C258
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KM4164
KM41C256
KM41C257
KM41C258
KM41C464
KM41C466
KM41C1000
KM41C1001
KM41C1002
KM44C256
toshiba 32k*8 sram
M5M23C100
M5M5265
seeq DQ2816A
M5M23C400
MB832001
HITACHI 64k DRAM
TC511000
TC51464
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STATIC RAM 8464
Abstract: IMS1433 SSM6116 IMS1630 SSM6171 SSM7188 hitachi selection guide SSM7164 hm6264 ic 6116 ram
Text: 16K Product S e le c tio n -C ro s s Reference Guide 16K Static RAM — Product Selection Typical Power mW Maximum Speed (ns) Part No/'» L7C167 Description Packages Available121 Com. Mil. Oper. Inactive Pins 8 10 135 75 20 DIP, LCC SOIC (Gull-Wing) SOJ (J-Lead)
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L7C167
L7C168
L7C170
L7C171
L7C172
L6116/
L6116L
L7C183
CY7C183
L7C184
STATIC RAM 8464
IMS1433
SSM6116
IMS1630
SSM6171
SSM7188
hitachi selection guide
SSM7164
hm6264
ic 6116 ram
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Untitled
Abstract: No abstract text available
Text: L7C183/184 2 x 4K x 16 Cache-Data Static RAM DESCRIPTION FEATURES □ 2 x 4K x 16 or 8K x 16 Cache-Data Static RAM with Direct Map or Two-Way Set Associative □ Auto-Powerdown Design □ Advanced CMOS Technology □ High Speed — to 20 ns worst-case □ Low Power Operation
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CY7C183/184
48-pin
52-pin
L7C183/184
Z0000Z00002Z>
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400X1
Abstract: CY7C183
Text: PRELIMINARY CYPRESS SEMICONDUCTOR Features • Pin-programmable into directmapped or two-way set-associative format • CMOS for optimum speed/power • High speed — 25 ns • Common I/O • Interna! address latch • TTL-compatible inputs and outputs • Capable o f withstanding greater than
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CY7C183
CY7C184
7C184-45LM
400X1
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Untitled
Abstract: No abstract text available
Text: LOGIC DEVICES INC 2bE D • SSbSTGS OGQlQib 3 ■ 2 x 4 K x 16 Cache-Data Static RAM DESCRIPTION FEATURES □ 2 x 4K x 16 or 8K x 16 Cache-Data Static RAM with Direct Map or Two-Way Set Associative □ Auto-Powerdown Design □ Advanced CMOS Technology
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CY7C183/184
48-pin
52-pin
L7C183/184
L7C183
L7C184
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8k x 16 bit ram
Abstract: No abstract text available
Text: PRELIMINARY CYPRESS SEMICONDUCTOR Features • Pin-program m able into directmapped or two-way set associative format • CM OS for optim um speed/power • High speed — 25 ns • Com m on I/O • Internal address latch • TTL-com patible inputs and outputs
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CY7C183
CY7C184
CY7C184-35LMB
CY7C184-45JC
CY7C184-45LMB
8-00090-A
8k x 16 bit ram
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CY7C169
Abstract: 54600
Text: Thermal Management CYPRESS Part Number CY7B173 CY7B174 CY7B180 CY7B181 CY7B185 CY7B186 CY7B191 CY7B192 CY7B194 CY7C122 CY7C123 CY7C128 CY7C128A CY7C130 CY7C131 CY7C132 CY7C136 CY7C140 CY7C141 CY7C142 CY7C146 CY7C147 CY7C148 CY7C149 CY7C150 CY7C157 CY7C161A
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CY7B173
CY7B174
CY7B180
CY7B181
CY7B185
CY7B186
CY7B191
CY7B192
CY7B194
CY7C122
CY7C169
54600
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