Untitled
Abstract: No abstract text available
Text: PTC Thermistor 2381 662 95xxx PTCHP12SxxxHYE FEATURES • Silver metallization suitable for clamping • Self-regulating temperature with no oscillation • Fast heat-up due to high dissipation at low temperatures • Dissipates up to 20 W depending on mounting conditions
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95xxx
PTCHP12SxxxHYE
2002/95/EC
2002/96/EC
03-May-07
VMN-PT0075-0710
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95xxx
Abstract: si3434 si3495
Text: Si3495DV Vishay Siliconix P-Channel 20-V D-S , 1.5-V (G-S) MOSFET FEATURES PRODUCT SUMMARY VDS (V) - 20 RDS(on) (Ω) ID (A) 0.024 at VGS = - 4.5 V -7 0.030 at VGS = - 2.5 V - 6.2 0.038 at VGS = - 1.8 V - 5.2 0.048 at VGS = - 1.5 V - 5.0 • Halogen-free According to IEC 61249-2-21
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Si3495DV
2002/95/EC
Si3495DV-T1-E3
Si3495DV-T1-GE3
95xxx
2011/65/EU
2002/95/EC.
2002/95/EC
2011/65/EU.
12-Mar-12
95xxx
si3434
si3495
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PDF
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XC9536XL
Abstract: XAPP114 XAPP427 XC9500XL XC9536 Pb-Free Marking Codes XC9536XL VQFP XC9536XL-10VQ64C VQG44 XC9536XL-10VQ44
Text: XC9536XL High Performance CPLD R DS058 v1.7 July 15, 2005 5 Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell
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XC9536XL
DS058
XC9500XL
220oC.
XAPP114
XAPP427
XC9536
Pb-Free Marking Codes
XC9536XL VQFP
XC9536XL-10VQ64C
VQG44
XC9536XL-10VQ44
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PDF
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95XXX
Abstract: Si3495DV Si3495DV-T1-GE3 V2500C
Text: Si3495DV Vishay Siliconix P-Channel 20-V D-S , 1.5-V (G-S) MOSFET FEATURES PRODUCT SUMMARY VDS (V) - 20 RDS(on) (Ω) ID (A) 0.024 at VGS = - 4.5 V -7 0.030 at VGS = - 2.5 V - 6.2 0.038 at VGS = - 1.8 V - 5.2 0.048 at VGS = - 1.5 V - 5.0 • Halogen-free According to IEC 61249-2-21
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Si3495DV
2002/95/EC
Si3495DV-T1-E3
Si3495DV-T1-GE3
95xxx
18-Jul-08
95XXX
V2500C
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PDF
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Untitled
Abstract: No abstract text available
Text: XC9536XV High-performance CPLD R DS053 v2.4 May 27, 2003 1 Features • • • • • • • • • 36 macrocells with 800 usable gates Available in small footprint packages - 44-pin PLCC (34 user I/O pins) - 44-pin VQFP (34 user I/O pins) - 48-pin CSP (36 user I/O pins)
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XC9536XV
DS053
44-pin
48-pin
54-input
220oC.
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PC44
Abstract: VQ44 XAPP361 XC9500XV XC9572XV
Text: XC9572XV High-performance CPLD R DS052 v2.5 August 21, 2003 5 Features • • • • • • • • 72 macrocells with 1,600 usable gates Available in small footprint packages - 44-pin PLCC (34 user I/O pins) - 44-pin VQFP (34 user I/O pins) - 48-pin CSP (38 user I/O pins)
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XC9572XV
DS052
44-pin
48-pin
100-pin
72-user
54-input
220oC.
PC44
VQ44
XAPP361
XC9500XV
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PDF
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XC9572XL
Abstract: xc9572xl pin configuration XC9572XL-5VQ44C XAPP114 XAPP427 XC9500XL XC9572 XC9572XL-10 XC9572XL-5 XC9572XL-7
Text: XC9572XL High Performance CPLD R DS057 v1.8 July 15, 2005 5 Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell
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Original
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XC9572XL
DS057
XC9500XL
220oC.
xc9572xl pin configuration
XC9572XL-5VQ44C
XAPP114
XAPP427
XC9572
XC9572XL-10
XC9572XL-5
XC9572XL-7
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PDF
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PC44
Abstract: XAPP361 XC9500XV XC9536XL XC9536XV B1.66 20E2
Text: XC9536XV High-performance CPLD R DS053 v2.5 August 21, 2003 1 Features • • • • • • • • • 36 macrocells with 800 usable gates Available in small footprint packages - 44-pin PLCC (34 user I/O pins) - 44-pin VQFP (34 user I/O pins) - 48-pin CSP (36 user I/O pins)
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XC9536XV
DS053
44-pin
48-pin
54-input
220oC.
PC44
XAPP361
XC9500XV
XC9536XL
B1.66
20E2
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PDF
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MOTOROLA smd SCR
Abstract: LA17 MC68SC302 SA16 SD15 93xxx FREE IC LM 4558 ci 45116 tic 47
Text: Freescale Semiconductor, Inc. Microprocessors and Memory Technologies Group Freescale Semiconductor, Inc. MC68SC302 Passive ISDN Protocol Engine User’s Manual Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
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MC68SC302
MC68SC302
MOTOROLA smd SCR
LA17
SA16
SD15
93xxx
FREE IC LM 4558
ci 45116
tic 47
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PDF
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952703BFLF
Abstract: ICS952703 sis741 952703BF
Text: ICS952703 Preliminary Product Preview Integrated Circuit Systems, Inc. Programmable Timing Control Hub for K7TM System Recommended Application: SiS741 style chipset with 964 South Bridge. Features/Benefits: • Selectable synchronous/asynchronous AGP/PCI frequency
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ICS952703
952703BF
952703BFLF
PVG48)
952703BFLFT
952703BFT
sis741
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PDF
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93C46 SOCKET
Abstract: CCMR 6 smd Ic BD 46 CL LA17 MC68SC302 SA16 SD15 ci 45116 4558 PIN DSA0039295
Text: Microprocessors and Memory Technologies Group MC68SC302 Passive ISDN Protocol Engine User’s Manual Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
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MC68SC302
MC68SC302
93C46 SOCKET
CCMR 6
smd Ic BD 46 CL
LA17
SA16
SD15
ci 45116
4558 PIN
DSA0039295
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PDF
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LA17
Abstract: MC68SC302 SA16 SD15 a 2231 93xxx cd 4074 B ic 4558 echo circuit diagram
Text: Freescale Semiconductor, Inc. Freescale Semiconductor, Inc. MC68SC302 Passive ISDN Protocol Engine User’s Manual 1997 Motorola, Inc. All Rights Reserved For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc.
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MC68SC302
CH370
MC68SC302
LA17
SA16
SD15
a 2231
93xxx
cd 4074 B
ic 4558 echo circuit diagram
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PDF
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XC9536-10PC44C
Abstract: No abstract text available
Text: XC9536 In-System Programmable CPLD R DS064 v6.0 June 18, 2003 5 Product Specification Features Description • • 5 ns pin-to-pin logic delays on all pins fCNT to 100 MHz • • • 36 macrocells with 800 usable gates Up to 34 user I/O pins 5V in-system programmable
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XC9536
DS064
36V18
XC9536-10PC44C
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PDF
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xilinx MARKING CODE
Abstract: No abstract text available
Text: XC9536XV High-performance CPLD R DS053 v2.7 January 16, 2006 1 Features • • • • • • • • • 36 macrocells with 800 usable gates Available in small footprint package - 44-pin VQFP (34 user I/O pins) Optimized for high-performance 2.5V systems
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XC9536XV
DS053
XC9500XV
220oC.
XCN05020.
xilinx MARKING CODE
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marking code f4 3 pin
Abstract: No abstract text available
Text: XC9572XV High-performance CPLD R DS052 v2.6 April 15, 2005 5 Product Specification Features • • • • • • • • PTOTAL = PINT + PIO = ICCINT x VCCINT + PIO 72 macrocells with 1,600 usable gates Available in small footprint packages - 44-pin PLCC (34 user I/O pins)
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XC9572XV
DS052
XC9500XV
220oC.
marking code f4 3 pin
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xc9572xl pin configuration
Abstract: XC9572XL XC9572XL-7VQ44I DS057 xc9572xl pin XC9572XL-10CS48C XAPP114 XC9500XL XC9572 XC9572XL-10
Text: XC9572XL High Performance CPLD R DS057 v1.4 August 21, 2003 5 Preliminary Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell
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Original
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XC9572XL
DS057
XC9500XL
220oC.
xc9572xl pin configuration
XC9572XL-7VQ44I
DS057
xc9572xl pin
XC9572XL-10CS48C
XAPP114
XC9572
XC9572XL-10
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PDF
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XC95XX
Abstract: XAPP361 XC9500XV XC9536XL XC9536XV XCN07010 xilinx MARKING CODE XCN05020 mclp
Text: XC9536XV High-performance CPLD R DS053 v3.0 June 25, 2007 1 Note: This product is being discontinued. You cannot order parts after May 14, 2008. Xilinx recommends replacing XC9536XV devices with equivalent XC9536XL devices in all designs as soon as possible. Recommended replacements are pin compatible, however require a VCC change to
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XC9536XV
DS053
XC9536XL
XCN07010
44-pin
220oC.
XCN05020.
XC95XX
XAPP361
XC9500XV
xilinx MARKING CODE
XCN05020
mclp
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PDF
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PCB BOARD LAYOUT
Abstract: connector pcb mounted PCB Layout straddle PCMCIA 68smx
Text: 68 Position PC Card Receptacles Methode’s 68 position receptacles are PCMCIA and JEIDA compatible and are available in straddle mount and single sided surface mount configurations. The independent dual beam contact design insures extended reliability, redundant electrical contact and consistent
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95X-XX-68STails
PCB BOARD LAYOUT
connector pcb mounted
PCB Layout
straddle PCMCIA
68smx
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PDF
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7400 series CMOS Logic ICs
Abstract: No abstract text available
Text: ICS952702 Integrated Circuit Systems, Inc. Programmable Timing Control Hub for K7TM System Recommended Application: SiS746/746FX style chipset Output Features: • 1 - Pair of differential open drain CPU outputs • 1 - Single-ended open drain CPU output •
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ICS952702
SiS746/746FX
48MHz
250ps
500ps
MO-118
ICS952702y
7400 series CMOS Logic ICs
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PDF
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sbx 1620
Abstract: L 7206 SBE160 95500-01 L7206 6363G1 261G2 LH-SBE320-SL 75XXX-XX 75500-01
Text: W i r v e r b i n d e n S i e Inhalt Allgemeines 3-5 SB Stecker SB 50, SB 175, SB 350 6-7 SBX Stecker SBX 175, SBX 350 8-9 SBE Stecker SBE 80, SBE 160, SBE 320 DIN-Stecker 14 - 15 säurebeständige DIN-Stecker 16 - 17 Powerpole Pak 18 - 19 Powerpole 20 - 21
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E6360G1
E6368G1
E6342G1
E6340G1
E6341G1
E6343G1
E6359G1
E6332G1
E6333G1
E6364G1
sbx 1620
L 7206
SBE160
95500-01
L7206
6363G1
261G2
LH-SBE320-SL
75XXX-XX
75500-01
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PDF
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Untitled
Abstract: No abstract text available
Text: Product Obsolete/Under Obsolescence XC9572XV High-performance CPLD R 5 Note: This product is being discontinued. You cannot order parts after May 14, 2008. Xilinx recommends replacing XC9572XV devices with equivalent XC9572XL devices in all designs as soon as possible. Recommended replacements are pin compatible, however require a VCC change to
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XC9572XV
DS052
XC9500XV
220oC.
XCN05020.
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xc9536
Abstract: xc9536-7vq44 95xxx XC9536-7VQ44I xc9536-15vq44i XC9536-15VQ44C
Text: XC9536 In-System Programmable CPLD R DS064 v6.2 April 15, 2005 5 Product Specification Features Description • • 5 ns pin-to-pin logic delays on all pins fCNT to 100 MHz • • • 36 macrocells with 800 usable gates Up to 34 user I/O pins 5V in-system programmable
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XC9536
DS064
36V18
xc9536-7vq44
95xxx
XC9536-7VQ44I
xc9536-15vq44i
XC9536-15VQ44C
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PDF
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xc9536
Abstract: XCN11010 xc9536 44 pin XILINX XC9536 xc9536 vqg44 xc9536-7vq44 XC9536-7VQG44I XC9536-7PCG44I XC9536-10VQ44C XC9536-15PCG44I
Text: – PRODUCT OBSOLETE / UNDER OBSOLESCENCE – XC9536 In-System Programmable CPLD R DS064 v7.0 May 17, 2013 5 Product Specification Features Description • • 5 ns pin-to-pin logic delays on all pins fCNT to 100 MHz • • • 36 macrocells with 800 usable gates
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XC9536
DS064
36V18
XCN11010
xc9536 44 pin
XILINX XC9536
xc9536 vqg44
xc9536-7vq44
XC9536-7VQG44I
XC9536-7PCG44I
XC9536-10VQ44C
XC9536-15PCG44I
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PDF
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Untitled
Abstract: No abstract text available
Text: 5 7 . SGS-THOMSON L lg iM M D Ê S M95640, M95320 M95160, M95080 64K/32K/16K/8K SERIAL SPI EEPROM with POSITIVE CLOCK STROBE PRELIMINARY DATA • 100,000 ERASE/WRITE CYCLES ■ 40 YEARS DATA RETENTION ■ SINGLE SUPPLY VOLTAGE - 4.5V to 5.5V for 95xxx - 2.5V to 5.5V for 95xxx-W
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OCR Scan
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M95640,
M95320
M95160,
M95080
64K/32K/16K/8K
M95xxx
M95xxx-W
M95xxx-R
M95xxx
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PDF
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