Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    8X4X32 Search Results

    8X4X32 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    ADSP-21160

    Abstract: ADSP-21161 ADSP-21364 CP-1201 ADSP-21364SBSQZENG tbdm
    Text: a SHARC Processor ADSP-21364 Preliminary Technical Data SUMMARY On-chip memory—3M bit of on-chip SRAM and a dedicated 4M bit of on-chip mask-programmable ROM Code compatible with all other members of the SHARC family The ADSP-21364 is available with a 333 MHz core instruction


    Original     		PDF ADSP-21364 ADSP-21364 32-bit/40-bit JESD51-9. JESD51-5. PR04624-0-10/04 ADSP-21160 ADSP-21161 CP-1201 ADSP-21364SBSQZENG tbdm

    ADSP-21367

    Abstract: ADSP-21368 CP-1201
    Text: a SHARC Processor ADSP-21368 Preliminary Technical Data SUMMARY Single-Instruction Multiple-Data SIMD computational architecture On-chip memory—2M bit of on-chip SRAM and a dedicated 6M bit of on-chip mask-programmable ROM Code compatible with all other members of the SHARC family


    Original     		PDF ADSP-21368 ADSP-21368 32-bit/40-bit Audi-21368SKBP-ENG 256-Lead PR05268-0-11/04 ADSP-21367 CP-1201

    Mobile Controlled Robot using DTMF applications

    Abstract: 5.1 home theatre circuit datasheet 5.1 home theater voice control robot fingerprint scanner circuit echo delay reverb 2164 dynamic ram ST EZ 728 218x example adsp-2186 instruction set
    Text: Table of Contents Introduction to ADI DSPs ADI DSP Key Benefits . 2 Markets & Example Applications . 4


    Original     		PDF ADSP-2100 16-Bit To-03 ADSP-21XX-DSW-ML ADSP-21XX-CTOOL-ML ADSP-21XX-CRTL-MAN ADSP-21XX-EZ-MAN ADSP-210XX-DSW-MAN ADSP-210XX-CTOOLML ADSP-210XX-CRTL-ML Mobile Controlled Robot using DTMF applications 5.1 home theatre circuit datasheet 5.1 home theater voice control robot fingerprint scanner circuit echo delay reverb 2164 dynamic ram ST EZ 728 218x example adsp-2186 instruction set

    interrupts for ADSP21369

    Abstract: control registers for ADSP-21369 JC JB jt boot kernel for the ADSP-21369 AD183x ADSP-21369
    Text: a SHARC Processor ADSP-21369 Preliminary Technical Data SUMMARY The ADSP-21369 is available with a 400 MHz core instruction rate with unique audio centric peripherals such as the Digital Audio Interface, S/PDIF transceiver, serial ports, 8channel asynchronous sample rate converter, precision


    Original     		PDF 32-bit/40-bit ADSP-21369 ADSP-21369 208-Lead 256-Ball PR05525-0-4/05 interrupts for ADSP21369 control registers for ADSP-21369 JC JB jt boot kernel for the ADSP-21369 AD183x

    AD150

    Abstract: No abstract text available
    Text: a SHARC Processor ADSP-21364 Preliminary Technical Data SUMMARY On-chip memory—3M bit of on-chip SRAM and a dedicated 4M bit of on-chip mask-programmable ROM Code compatible with all other members of the SHARC family The ADSP-21364 is available with a 333 MHz core instruction


    Original     		PDF 32-bit/40-bit ADSP-21364 32-bit floating-point/32-bit fixed-point/40-bit ADSP-21364 JESD51-9. JESD51-5. AD150

    ADSP-21065L

    Abstract: ADSP21065LKS200X KHQD TMS 3727
    Text:  DSP Microcomputer ADSP-21065L Preliminary Technical Information ‡ +  ,QVWUXPHQWDWLRQDQG,QGXVWULDO$SSOLFDWLRQV ‡ 6XSHU+DUYDUG$UFKLWHFWXUH&RPSXWHU 6+$5&  RXU,QGHSHQGHQW%XVHVIRU'XDO'DWD


    Original     		PDF ADSP-21065L KLS65 00HPRU\DQG 23HULSKHUDO 66XSSRUWIRU6LPXOWDQHRXV5HFHLYHDQG7UDQVPLW /2363HDN0 /2366XVWDLQHG3HUIRUPDQFH 00HPRU\ ADSP-21065LKS-200x ADSP-21065L ADSP21065LKS200X KHQD TMS 3727

    sharc ADSP-21xxx general block diagram

    Abstract: block diagram of ADSP21xxx SHARC processor sharc 21xxx architecture block diagram 4x4 barrel shifter sharc ADSP-21xxx architecture diagram sharc ADSP21xxx architecture ADSP-21160 ADSP-21161 ADSP-21266 JC JB jt
    Text: PRELIMINARY TECHNICAL DATA S a High Performance SHARC Audio Processor ADSP-21266 Preliminary Technical Data SUMMARY High performance 32-bit/40-bit floating point processor optimized for audio processing The ADSP-21266 processes high performance audio while enabling low system costs


    Original     		PDF ADSP-21266 32-bit/40-bit ADSP-21266 96kHz, 32-bit floating-point/32-bit 40-bit sharc ADSP-21xxx general block diagram block diagram of ADSP21xxx SHARC processor sharc 21xxx architecture block diagram 4x4 barrel shifter sharc ADSP-21xxx architecture diagram sharc ADSP21xxx architecture ADSP-21160 ADSP-21161 JC JB jt

    block diagram of ADSP21xxx SHARC processor

    Abstract: sharc ADSP-21xxx general block diagram sharc ADSP-21xxx architecture diagram ADSP-21160 ADSP-21161 ADSP-21262 sharc ADSP-21xxx architecture INSTRUCTION SET JC JB jt
    Text: PRELIMINARY TECHNICAL DATA S a High Performance Floating-Point Processor ADSP-21262 Preliminary Technical Data SUMMARY High performance 32-bit floating-point processor optimized for high precision signal processing applications Single-Instruction Multiple-Data SIMD computational


    Original     		PDF ADSP-21262 32-bit floating-point/32-bit point/40-bit block diagram of ADSP21xxx SHARC processor sharc ADSP-21xxx general block diagram sharc ADSP-21xxx architecture diagram ADSP-21160 ADSP-21161 ADSP-21262 sharc ADSP-21xxx architecture INSTRUCTION SET JC JB jt

    ADSP-21160

    Abstract: KLS65
    Text:   DSP Microcomputer ADSP-21160 Preliminary Technical Data 6800$5< . < ($785(6 ‡ ‡ ‡ ‡ ‡ y r a n i l m a i l c i e Pr chn a Te Dat ‡ ‡ ‡ ‡ ‡ DUAL-PORTED SRAM CORE PROCESSOR TIMER INSTRUCTION CACHE TWO INDEPENDENT DUAL-PORTED BLOCKS 32 x 48-BIT


    Original     		PDF ADSP-21160 48-BIT 8x4x32 /236SHDNDQG0 63LVWREHGHWHUPLQHG ADSP-21160 KLS65

    dts master audio DL 1200

    Abstract: 3x3 bit parallel multiplier 4604 CMOS Dolby prologic ADSP21365 ADSP-21365 CP-1201
    Text: a SHARC Processor ADSP-21365/ADSP-21366 Preliminary Technical Data SUMMARY Single-Instruction Multiple-Data SIMD computational architecture On-chip memory—3M bit of on-chip SRAM and a dedicated 4M bit of on-chip mask-programmable ROM Code compatible with all other members of the SHARC family


    Original     		PDF ADSP-21365/ADSP-21366 ADSP-21365/6 ADSP21365 32-bit/40-beat JESD51-5. ADSP-21365/6 PR04625-0-10/04 dts master audio DL 1200 3x3 bit parallel multiplier 4604 CMOS Dolby prologic ADSP-21365 CP-1201

    Untitled

    Abstract: No abstract text available
    Text: SHARC Processor ADSP-21267 Preliminary Technical Data SUMMARY DAI incorporates two Precision Clock Generators PCG , and an Input Data Port (IDP) that includes a Parallel Data Acquisition Port (PDAP), and three programmable timers, all under software control by the Signal Routing Unit (SRU)


    Original     		PDF ADSP-21267 ADSP-21267 32-bit/40-bit 144-Lead 136-Lead

    ADSP21267

    Abstract: ADSP-21267
    Text: SHARC Processor ADSP-21267 Preliminary Technical Data SUMMARY DAI incorporates two precision clock generators PCG , and an input data port (IDP) that includes a parallel data acquisition port (PDAP), and three programmable timers, all under software control by the signal routing unit (SRU)


    Original     		PDF ADSP-21267 ADSP-21267 32-bit/40-bit 144-Lead 136-Lead PR04623-0-1/04 ADSP21267

    dc-ac inverter PURE SINE WAVE schematic diagram

    Abstract: mp3 player schematic diagram 5.1 home theatre circuit diagram for project AD9042 MIP 2f2 permanent magnet synchronous generator 2MW PWM matlab Toshiba MRI Scanner ad7730 pcb circuit example 49mhz remote control transmitter circuit
    Text: MIXED-SIGNAL AND DSP DESIGN TECHNIQUES a ANALOG DEVICES TECHNICAL REFERENCE BOOKS PUBLISHED BY PRENTICE HALL Analog-Digital Conversion Handbook Digital Signal Processing Applications Using the ADSP-2100 Family Volume 1:1992, Volume 2:1994 Digital Signal Processing in VLSI


    Original     		PDF ADSP-2100 ADSP-2101 ADSP-21000 IADSP-2116x, ADSP-2181/3, ADSP-2183, ADSP-2184/L, ADSP-2185/L/M, ADSP-2185L/86L, dc-ac inverter PURE SINE WAVE schematic diagram mp3 player schematic diagram 5.1 home theatre circuit diagram for project AD9042 MIP 2f2 permanent magnet synchronous generator 2MW PWM matlab Toshiba MRI Scanner ad7730 pcb circuit example 49mhz remote control transmitter circuit

    register file

    Abstract: ADSP-2100 ADSP-21000 ADSP-21160 RND32
    Text:  '$7$$&& 66(6 Figure 5-0. Table 5-0. Listing 5-0. 2YHUYLHZ The ADSP-21160’s 64-bit data width DM and PM buses provide support for a broad range of register load/store data access options. Since the typical data width supported by the ADSP-21160 architecture is 32-bits, the


    Original     		PDF ADSP-21160s 64-bit ADSP-21160 32-bits, 40-bit register file ADSP-2100 ADSP-21000 RND32

    AD150

    Abstract: ADSP-21160 ADSP-21161 ADSP-21364 CP-1201 sharc iir filter ADSP 21364 sport control register
    Text: a SHARC Processor ADSP-21364 Preliminary Technical Data SUMMARY On-chip memory—3M bit of on-chip SRAM and a dedicated 4M bit of on-chip mask-programmable ROM Code compatible with all other members of the SHARC family The ADSP-21364 is available with a 333 MHz core instruction


    Original     		PDF ADSP-21364 ADSP-21364 32-bit/40-bit JESD51-9. JESD51-5. PR04624-0-2/05 AD150 ADSP-21160 ADSP-21161 CP-1201 sharc iir filter ADSP 21364 sport control register

    627M

    Abstract: sharc ADSP-21xxx general block diagram schottky k04 21161n PIN HEADER 4X1, 2.54 pitch Pin Header
    Text: S DSP Microcomputer ADSP-21161N a SUMMARY Integrated Peripherals—Integrated I/O Processor, 1 Mbit High Performance 32-Bit DSP—Applications in Audio, On-Chip Dual-Ported SRAM, SDRAM Controller, Medical, Military, Wireless Communications, Glueless Multiprocessing Features, and I/O Ports


    Original     		PDF ADSP-21161N 32-Bit ADSP-21161N 40-Bit MO-151. ADSP-21161NKCA-100 ADSP-21161NCCA-100 225-lead 627M sharc ADSP-21xxx general block diagram schottky k04 21161n PIN HEADER 4X1, 2.54 pitch Pin Header

    three phase inverters circuit diagram

    Abstract: No abstract text available
    Text: a SHARC Processor ADSP-21367 Preliminary Technical Data SUMMARY Single-Instruction Multiple-Data SIMD computational architecture On-chip memory—2M bit of on-chip SRAM and a dedicated 6M bit of on-chip mask-programmable ROM Code compatible with all other members of the SHARC family


    Original     		PDF 32-bit/40-bit 32-bit 208-Lead 256-Ball ADSP-21367 PR05267-0-6/05 three phase inverters circuit diagram

    Untitled

    Abstract: No abstract text available
    Text: a SHARC Processor ADSP-21375 Preliminary Technical Data SUMMARY High performance 32-bit/40-bit floating point processor optimized for high performance audio processing Single-instruction, multiple-data SIMD computational architecture On-chip memory—0.5M bit of on-chip SRAM and a dedicated


    Original     		PDF 32-bit/40-bit ADSP-21375 ADSP-21375 48-BIT MS-029, 208-Lead S-208-2) ADSP-21375KSZ-ENG1 S-208-2

    IIR SIMD

    Abstract: ADSP-21365 CP-1201 ADSP-21160 ADSP-21161
    Text: SHARC Processor ADSP-21365 Preliminary Technical Data SUMMARY On-chip memory—3 Mbits of on-chip SRAM and a dedicated 4 Mbits of on-chip mask-programmable ROM Code compatible with all other members of the SHARC family The ADSP-21365 is available in a 300 MHz core instruction


    Original     		PDF ADSP-21365 ADSP-21365 32-bit/40-bit 32-bit 136-Lead IIR SIMD CP-1201 ADSP-21160 ADSP-21161

    ADSP-21160

    Abstract: ADSP-21161 ADSP-21364 hardware design for DC MOTOR SPEED CONTROL USING
    Text: SHARC Processor ADSP-21364 Preliminary Technical Data SUMMARY Code compatible with all other members of the SHARC family The ADSP-21364 is available in a 300 MHz core instruction rate. For complete ordering information, see Ordering Guide on page 43 High performance 32-bit/40-bit floating point processor


    Original     		PDF ADSP-21364 ADSP-21364 32-bit/40-bit Hz/1800 ADSP-21364SKBC-ENG 136-Lead PR04624-0-1/04 ADSP-21160 ADSP-21161 hardware design for DC MOTOR SPEED CONTROL USING

    ADSP2116x

    Abstract: No abstract text available
    Text: DSP Microcomputer ADSP-21160 a Preliminary Technical Data SUMMARY • • • • • • • • • • DUAL-PORTED SRAM CO RE PROCESSO R TI MER 100 MHz, 10 ns core instruction rate Single-cycle instruction execution, including SIMD operations in both computational units


    Original     		PDF ADSP-21160 32-bit ADSP-2106x ADSP-21160MKB-100 400-lead ADSP2116x

    NK 90 YHG

    Abstract: 43E-14 ADSP-21060 ADSP-21061 ADSP-21062 ADSP-21065L ADSP-21160 ADSP-21161N 254ME fixed point iir filter
    Text: DSP Microcomputer ADSP-21161N a Preliminary Technical Data SUMMARY • • • C O R E P R O C E S SO R T IM E R • KEY FEATURES • • • • • 100 MHz 10 ns core instruction rate Single-cycle instruction execution, including SIMD operations in both computational units


    Original     		PDF ADSP-21161N 225-ball 17x17mm 8x4x32 ADSP-21161N-KB-100X 225-lead NK 90 YHG 43E-14 ADSP-21060 ADSP-21061 ADSP-21062 ADSP-21065L ADSP-21160 ADSP-21161N 254ME fixed point iir filter

    schottky k04

    Abstract: ADSP-21160 ADSP-21160M ADSP-21160N ADSP-21161 986 t04
    Text: PRELIMINARY TECHNICAL DATA a DSP Microcomputer ADSP-21160N Preliminary Technical Data SUMMARY High-Performance 32-Bit DSP—Applications in Audio, Medical, Military, Graphics, Imaging, and Communication Super Harvard Architecture—Four Independent Buses for Dual Data Fetch, Instruction Fetch, and


    Original     		PDF ADSP-21160N 32-Bit ADSP-2106x ADSP-21160NCB-TBD ADSP-21160NKB-95 schottky k04 ADSP-21160 ADSP-21160M ADSP-21160N ADSP-21161 986 t04

    ADSP-21160

    Abstract: ADSP-21371 ADSP-21375 CP-1201
    Text: a SHARC Processor ADSP-21371 Preliminary Technical Data SUMMARY High performance 32-bit/40-bit floating point processor optimized for high performance audio processing Single-instruction, multiple-data SIMD computational architecture On-chip memory—1M bit of on-chip SRAM and a dedicated


    Original     		PDF ADSP-21371 32-bit/40-bit ADSP-21371 MS-029, 208-Lead S-208-2) ADSP-21371KSZ-ENG1 S-208-2 ADSP-21160 ADSP-21375 CP-1201