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    74AUP2G17GF Search Results

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    74AUP2G17GF Price and Stock

    Rochester Electronics LLC 74AUP2G17GF,132

    IC BUFFER NON-INVERT 3.6V 6XSON
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    DigiKey 74AUP2G17GF,132 Bulk 1,629
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    Nexperia 74AUP2G17GF,132

    IC BUFFER NON-INVERT 3.6V 6XSON
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    DigiKey 74AUP2G17GF,132 Reel 5,000
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    Avnet Americas 74AUP2G17GF,132 Reel 5,000
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    NXP Semiconductors 74AUP2G17GF,132

    Schmitt Trigger Buffer 2-CH Non-Inverting CMOS 6-Pin XSON T/R
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    Verical 74AUP2G17GF,132 114,850 1,994
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    74AUP2G17GF,132 95,000 1,994
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    74AUP2G17GF,132 89,333 1,994
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    Rochester Electronics 74AUP2G17GF,132 299,183 1
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    74AUP2G17GF Datasheets (4)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    74AUP2G17GF NXP Semiconductors Low-power dual Schmitt trigger Original PDF
    74AUP2G17GF NXP Semiconductors 74AUP2G17 - IC AUP/ULP/V SERIES, DUAL 1-INPUT NON-INVERT GATE, PDSO6, 1 X 1 MM, 0.50 MM HEIGHT, PLASTIC, SOT-891, SON-6, Gate Original PDF
    74AUP2G17GF,132 NXP Semiconductors Low-power dual Schmitt trigger; Package: SOT891 (XSON6); Container: Tape reel smd Original PDF
    74AUP2G17GF,132 NXP Semiconductors 74AUP2G17 - IC AUP/ULP/V SERIES, DUAL 1-INPUT NON-INVERT GATE, PDSO6, 1 X 1 MM, 0.50 MM HEIGHT, PLASTIC, SOT-891, XSON-6, Gate Original PDF

    74AUP2G17GF Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: 74AUP2G17 Low-power dual Schmitt trigger Rev. 5 — 5 December 2011 Product data sheet 1. General description The 74AUP2G17 provides two Schmitt trigger buffers. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.


    Original
    PDF 74AUP2G17 74AUP2G17

    74AUP2G17

    Abstract: 74AUP2G17GF 74AUP2G17GM 74AUP2G17GW
    Text: 74AUP2G17 Low-power dual Schmitt trigger Rev. 4 — 3 November 2010 Product data sheet 1. General description The 74AUP2G17 provides two Schmitt trigger buffers. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.


    Original
    PDF 74AUP2G17 74AUP2G17 74AUP2G17GF 74AUP2G17GM 74AUP2G17GW

    Untitled

    Abstract: No abstract text available
    Text: 74AUP2G17 Low-power dual Schmitt trigger Rev. 6 — 4 December 2012 Product data sheet 1. General description The 74AUP2G17 provides two Schmitt trigger buffers. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.


    Original
    PDF 74AUP2G17 74AUP2G17

    marking code pv

    Abstract: No abstract text available
    Text: 74AUP2G17 Low-power dual Schmitt trigger Rev. 01 — 7 November 2006 Product data sheet 1. General description The 74AUP2G17 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. This device ensures a very low static and dynamic power consumption across the entire


    Original
    PDF 74AUP2G17 74AUP2G17 marking code pv

    Untitled

    Abstract: No abstract text available
    Text: 74AUP2G17 Low-power dual Schmitt trigger Rev. 5 — 5 December 2011 Product data sheet 1. General description The 74AUP2G17 provides two Schmitt trigger buffers. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.


    Original
    PDF 74AUP2G17 74AUP2G17

    74AUP2G17

    Abstract: 74AUP2G17GF 74AUP2G17GM 74AUP2G17GW JESD22-A114E
    Text: 74AUP2G17 Low-power dual Schmitt trigger Rev. 03 — 6 July 2009 Product data sheet 1. General description The 74AUP2G17 provides two Schmitt trigger buffers. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.


    Original
    PDF 74AUP2G17 74AUP2G17 74AUP2G17GF 74AUP2G17GM 74AUP2G17GW JESD22-A114E

    74AUP2G17

    Abstract: 74AUP2G17GF 74AUP2G17GM 74AUP2G17GW JESD22-A114E
    Text: 74AUP2G17 Low-power dual Schmitt trigger Rev. 02 — 10 January 2008 Product data sheet 1. General description The 74AUP2G17 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. This device ensures a very low static and dynamic power consumption across the entire


    Original
    PDF 74AUP2G17 74AUP2G17 74AUP2G17GF 74AUP2G17GM 74AUP2G17GW JESD22-A114E