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    74HCT27 Search Results

    74HCT27 Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    CD74HCT273M96 Texas Instruments High Speed CMOS Logic Octal D-Type Flip-Flop with Reset 20-SOIC -55 to 125 Visit Texas Instruments Buy
    SN74HCT273N Texas Instruments Octal D-Type Flip-Flops With Clear 20-PDIP -40 to 85 Visit Texas Instruments Buy
    CD74HCT27M96 Texas Instruments High Speed CMOS Logic Triple 3-Input NOR Gates 14-SOIC -55 to 125 Visit Texas Instruments Buy
    SN74HCT273DWRG4 Texas Instruments Octal D-Type Flip-Flops With Clear 20-SOIC -40 to 85 Visit Texas Instruments Buy
    SN74HCT273PWR Texas Instruments Octal D-Type Flip-Flops With Clear 20-TSSOP -40 to 85 Visit Texas Instruments Buy
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    74HCT27 Price and Stock

    Texas Instruments SN74HCT273PWR

    IC FF D-TYPE SNGL 8BIT 20TSSOP
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    Texas Instruments SN74HCT273NSR

    IC FF D-TYPE SNGL 8BIT 20SO
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    Texas Instruments CD74HCT27M96

    IC GATE NOR 3CH 3-INP 14SOIC
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    Rochester Electronics CD74HCT27M96 2,200 1
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    Nexperia 74HCT27D,653

    IC GATE NOR 3CH 3-INP 14SO
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    Nexperia 74HCT273D,653

    IC FF D-TYPE SNGL 8BIT 20SO
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    74HCT27 Datasheets (112)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    74HCT27 Philips Semiconductors Triple 3-Input NOR Gate Original PDF
    74HCT273 Philips Semiconductors Octal D-type flip-flop with reset positive-edge trigger Original PDF
    74HCT273 Supertex Octal D Flip-Flop with Clear Scan PDF
    74HCT273BQ Philips Semiconductors 74HC/HCT273, Octal D-type flip-flop with reset, positive-edge trigger Original PDF
    74HCT273BQ,115 NXP Semiconductors 74HCT273 - IC HCT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PQCC20, 2.50 X 4.50 MM, 0.85 MM HEIGHT, PLASTIC, MO-241, SOT-764-1, DHVQFN-20, FF/Latch Original PDF
    74HCT273BQ,115 NXP Semiconductors Octal D-type flip-flop with reset; positive-edge trigger - Description: D-Type Flip-Flop with Reset; Positive-Edge Trigger; TTL Enabled ; Fmax: 36 MHz; Logic switching levels: TTL ; Number of pins: 20 ; Output drive capability: +/- 4 mA ; Power dissipation considerations: Low Power ; Propagation delay: 15 ns; Voltage: 4.5-5.5V; Package: SOT764-1 (DHVQFN20); Container: Reel Pack, SMD, 7" Original PDF
    74HCT273BQ-G NXP Semiconductors 74HCT273BQ - Octal D-type flip-flop with reset; positive-edge trigger - Description: D-Type Flip-Flop with Reset; Positive-Edge Trigger; TTL Enabled ; Fmax: 36 MHz; Logic switching levels: TTL ; Number of pins: 20 ; Output drive capability: +/- 4 mA ; Power dissipation considerations: Low Power ; Propagation delay: 15 ns; Voltage: 4.5-5.5V Original PDF
    74HCT273BQ-G NXP Semiconductors Octal D-type flip-flop with reset; positive-edge trigger - Description: D-Type Flip-Flop with Reset; Positive-Edge Trigger; TTL Enabled ; Fmax: 36 MHz; Logic switching levels: TTL ; Number of pins: 20 ; Output drive capability: +/- 4 mA ; Power dissipation considerations: Low Power ; Propagation delay: 15 ns; Voltage: 4.5-5.5V Original PDF
    74HCT273BQ-Q100X NXP Semiconductors 74HCT273BQ-Q100 - 74HCT273BQ-Q100 - Octal D-type flip-flop with reset; positive-edge trigger Original PDF
    74HCT273D NXP Semiconductors Octal D-type flip-flop with reset; positive-edge trigger Original PDF
    74HCT273D Philips Semiconductors Octal D-type flip-flop with reset positive-edge trigger Original PDF
    74HCT273D Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    74HCT273D Philips Semiconductors Octal D-Type Flip-Flop with Reset, Positive-Edge Trigger Scan PDF
    74HCT273D,652 NXP Semiconductors 74HCT273 - IC HCT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20, 7.50 MM, PLASTIC, MS-013, SOT-163-1, SOP-20, FF/Latch Original PDF
    74HCT273D,652 NXP Semiconductors Octal D-type flip-flop with reset; positive-edge trigger - Description: D-Type Flip-Flop with Reset; Positive-Edge Trigger; TTL Enabled ; Fmax: 36 MHz; Logic switching levels: TTL ; Number of pins: 20 ; Output drive capability: +/- 4 mA ; Power dissipation considerations: Low Power ; Propagation delay: 15 ns; Voltage: 4.5-5.5V; Package: SOT163-1 (SO20); Container: Bulk Pack, CECC Original PDF
    74HCT273D,653 NXP Semiconductors 74HCT273 - IC HCT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20, 7.50 MM, PLASTIC, MS-013, SOT-163-1, SOP-20, FF/Latch Original PDF
    74HCT273D,653 NXP Semiconductors Octal D-type flip-flop with reset; positive-edge trigger - Description: D-Type Flip-Flop with Reset; Positive-Edge Trigger; TTL Enabled ; Fmax: 36 MHz; Logic switching levels: TTL ; Number of pins: 20 ; Output drive capability: +/- 4 mA ; Power dissipation considerations: Low Power ; Propagation delay: 15 ns; Voltage: 4.5-5.5V; Package: SOT163-1 (SO20); Container: Reel Pack, SMD, 13", CECC Original PDF
    74HCT273D/AUJ NXP Semiconductors Logic - Flip Flops, Integrated Circuits (ICs), IC FLIP-FLOP OCT D POS 20SOIC Original PDF
    74HCT273DB NXP Semiconductors Octal D-type flip-flop with reset; positive-edge trigger Original PDF
    74HCT273DB Philips Semiconductors Octal D-type flip-flop with reset positive-edge trigger Original PDF

    74HCT27 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    74HC27

    Abstract: dhvqfn14 74HC27N 74HC27BQ 74HC27D 74HC27DB 74HC27PW 74HCT27 JESD22-A114E HCT273
    Text: 74HC27; 74HCT27 Triple 3-input NOR gate Rev. 03 — 7 January 2008 Product data sheet 1. General description The 74HC27; 74HCT27 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL LSTTL . The 74HC27; 74HCT27 provides the 3-input NOR function.


    Original
    PDF 74HC27; 74HCT27 74HCT27 JESD22-A114E JESD22-A115-A 74HC27N DIP14 74HC27 dhvqfn14 74HC27N 74HC27BQ 74HC27D 74HC27DB 74HC27PW HCT273

    74hc273

    Abstract: harris hct273
    Text: [ /Title CD74 HC273 , CD74 HCT27 3 /Subject (High Speed CMOS Logic Octal DType Flip- CD54/74HC273, CD54/74HCT273 Data sheet acquired from Harris Semiconductor SCHS174A High Speed CMOS Logic Octal D-Type Flip-Flop with Reset February 1998 - Revised May 2000


    Original
    PDF SCHS174A CD54/74HC273, CD54/74HCT273 HC273 HCT273 59628772501RA CD54HCT273F CD54HCT273F3A 5962View 8772501RA 74hc273 harris hct273

    Untitled

    Abstract: No abstract text available
    Text: 74HC27; 74HCT27 Triple 3-input NOR gate Rev. 03 — 7 January 2008 Product data sheet 1. General description The 74HC27; 74HCT27 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL LSTTL . The 74HC27; 74HCT27 provides the 3-input NOR function.


    Original
    PDF 74HC27; 74HCT27 74HCT27 JESD22-A114E JESD22-A115-A 74HC27N DIP14

    Untitled

    Abstract: No abstract text available
    Text: [ /Title CD74 HC27, CD74 HCT27 /Subject (High Speed CMOS Logic CD54/74HC27, CD54/74HCT27 Data sheet acquired from Harris Semiconductor SCHS132A High Speed CMOS Logic Triple 3-Input NOR Gate August 1997 - Revised May 2000 Features Description • Buffered Inputs


    Original
    PDF CD54/74HC27, CD54/74HCT27 SCHS132A HCT27 SDYA012 SN54/74HCT SCLA011 SCLA008 SZZU001B, SDYU001N,

    74HC273

    Abstract: 74hct273
    Text: [ /Title CD74 HC273 , CD74 HCT27 3 /Subject (High Speed CMOS Logic Octal DType Flip- CD54/74HC273, CD54/74HCT273 Data sheet acquired from Harris Semiconductor SCHS174A High Speed CMOS Logic Octal D-Type Flip-Flop with Reset February 1998 - Revised May 2000


    Original
    PDF HC273 HCT27 CD54/74HC273, CD54/74HCT273 SCHS174A HC273 HCT273 74HC273 74hct273

    74HC273

    Abstract: HCT273 74HC273N TSSOP20 Package 74HCT273 SO20 Package SSOP20 package 74HC273BQ 74HC273D 74HC273DB
    Text: 74HC273; 74HCT273 Octal D-type flip-flop with reset; positive-edge trigger Rev. 03 — 24 January 2006 Product data sheet 1. General description The 74HC273; 74HCT273 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL LSTTL .


    Original
    PDF 74HC273; 74HCT273 74HCT273 HCT273 74HC273 74HC273N TSSOP20 Package SO20 Package SSOP20 package 74HC273BQ 74HC273D 74HC273DB

    Untitled

    Abstract: No abstract text available
    Text: [ /Title CD74 HC27, CD74 HCT27 /Subject (High Speed CMOS Logic CD54/74HC27, CD54/74HCT27 Data sheet acquired from Harris Semiconductor SCHS132A High Speed CMOS Logic Triple 3-Input NOR Gate August 1997 - Revised May 2000 Features Description • Buffered Inputs


    Original
    PDF CD54/74HC27, CD54/74HCT27 SCHS132A HCT27 59628970301CA CD54HCT27F3A 5962View 8970301CA

    Untitled

    Abstract: No abstract text available
    Text: 74HC273-Q100; 74HCT273-Q100 Octal D-type flip-flop with reset; positive-edge trigger Rev. 1 — 19 June 2013 Product data sheet 1. General description The 74HC273-Q100; 74HCT273-Q100 is an octal positive-edge triggered D-type flip-flop. The device features clock CP and master reset (MR) inputs. The outputs Qn assume the


    Original
    PDF 74HC273-Q100; 74HCT273-Q100 74HCT273-Q100 HCT273

    harris 74hct27

    Abstract: CD54HC27F3A CD54HCT27F3A CD74HC27E CD74HC27M CD74HCT27E
    Text: [ /Title CD74 HC27, CD74 HCT27 /Subject (High Speed CMOS Logic CD54/74HC27, CD54/74HCT27 Data sheet acquired from Harris Semiconductor SCHS132A High Speed CMOS Logic Triple 3-Input NOR Gate August 1997 - Revised May 2000 Features Description • Buffered Inputs


    Original
    PDF HCT27 CD54/74HC27, CD54/74HCT27 SCHS132A HCT27 harris 74hct27 CD54HC27F3A CD54HCT27F3A CD74HC27E CD74HC27M CD74HCT27E

    74HC27

    Abstract: 74HCT27P
    Text: 74HC27; 74HCT27 Triple 3-input NOR gate Rev. 4 — 5 June 2013 Product data sheet 1. General description The 74HC27; 74HCT27 is a triple 3-input NOR gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of


    Original
    PDF 74HC27; 74HCT27 74HCT27 74HC27: 74HCT27: JESD22-A114F JESD22-A115-A 74HC27N 74HCT27N 74HC27 74HCT27P

    Untitled

    Abstract: No abstract text available
    Text: 74HC27-Q100; 74HCT27-Q100 Triple 3-input NOR gate Rev. 1 — 3 June 2013 Product data sheet 1. General description The 74HC27-Q100; 74HCT27-Q100 is a triple 3-input NOR gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in


    Original
    PDF 74HC27-Q100; 74HCT27-Q100 74HCT27-Q100 AEC-Q100 74HC27-Q100:

    Untitled

    Abstract: No abstract text available
    Text: Technical Data CD54/74HC273 CD54/74HCT273 File Number 1479 High-Speed CMOS Logic Octal D Flip-Flop with Reset Type Features: • Common clock and asynchronous master reset ■ Positive-edge triggering ■ Buffered inputs ■ Typical fmat — 60 MHz @ Vcc ~ 5 V, C l = 15pF, 7a = 25° C


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    PDF CD54/74HC273 CD54/74HCT273 54/74H

    74HC273

    Abstract: 74HCT273
    Text: G E SOLI» STATE 01 D E | 3Û7S0Ô1 001175=1 4 Technical Data. T-46-07-05 CD54/74HC273 CD54/74HCT273 File Number 1479 High-Speed CMOS Logic Octal D Flip-Flop with Reset Type Features: • Common clock and asynchronous master reset ■ Positive-edge triggering


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    PDF T-46-07-05 CD54/74HC273 CD54/74HCT273 92C3-36976R2 vce--------------90% 74HCT 92CS-360B5 74HC273 74HCT273

    Untitled

    Abstract: No abstract text available
    Text: GD54/74HC273, GD54/74HCT273 OCTAL D-TYPE FLIP-FLOPS WITH COMMON CLOCK & CLEAR General Description These devices are identical in pinout to the 5 4 /7 4 L S 2 7 3 . They consist of eight master/slave D- Pin Configuration type flip-flops with a common Clock and common


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    PDF GD54/74HC273, GD54/74HCT273

    74HC273

    Abstract: 74hct273 74LS273 74HC GD74HC273 pin diagram of 74ls273 GD74HC27 OT273
    Text: GD54/74HC273, GD54/74HCT273 OCTAL D-TYPE FLIP-FLOPS WITH COMMON CLOCK & CLEAR General Description These devices are identical in pinout to the 5 4 /7 4 L S 2 7 3 . They consist of eight master/slave D- Pin Configuration type flip-flops with a common Clock and common


    OCR Scan
    PDF GD54/74HC273, GD54/74HCT273 54/74LS273. H02A757 74HC273 74hct273 74LS273 74HC GD74HC273 pin diagram of 74ls273 GD74HC27 OT273

    54HCT273

    Abstract: 74HCT273 J131 D FLIPFLOP PIN CONFIGURATION flip-flop 74HCT 74SC273 flip-flop JT
    Text: ^ S u p e r Z e x in c . HCT/SC273 O '.ta i D F lip F lo p W it h C le a r »Preliminary Military 54HCT High Speed (74HCT) Standard (74SC) Octal D flip-flop with Clear 74HCT273 74SC273 54HCT273 Operating temperature range ( ° C) - 4 0 to + 8 5 - 4 0 to + 8 5


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    PDF HCT/SC273 74HCT) 54HCT) 74HCT273 74SC273 54HCT273 54/74LS 10/jA 54HCT273 J131 D FLIPFLOP PIN CONFIGURATION flip-flop 74HCT flip-flop JT

    Untitled

    Abstract: No abstract text available
    Text: GD54/74HC27, GD54/74HCT27 TRIPLE 3-INPUT NOR GATES General Description Pin Configuration These devices are identical in pinout to the 5 4 /7 4 L S 2 7 . They contain three independent 3-input NOR gates. These devices are characteriz­ ed for operation over wide temperature ranges to


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    PDF GD54/74HC27, GD54/74HCT27

    74hc273

    Abstract: 54HC273 74HCT273
    Text: Technical Data, CD54/74HC273 CD54/74HCT273 File Number 1479 High-Speed CMOS Logic Octal D Flip-Flop with Reset Type Features: • Comm on clock and asynchronous master reset • Positive-edge triggering ■ Buffered inputs ■ Typical fm,K = 60 M H z 'SET


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    PDF CD54/74HC273 CD54/74HCT273 54/74H 74hc273 54HC273 74HCT273

    74hct273

    Abstract: No abstract text available
    Text: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Octal D Flip-Flop with Common Clock and Reset with LSTTL Compatible Inputs MC54/74HCT273A High-Performance Silicon-Gate CMOS The M C54/74HCT273A may be used as a level converter for interfacing TTL or NMOS outputs to High-Speed CMOS inputs.


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    PDF C54/74HCT273A HCT273A LS273. Requirement125 MC54/74HCT273A 74hct273

    Untitled

    Abstract: No abstract text available
    Text: Technical Data CD54/74HC27 CD54/74HCT27 File N um ber 1648 High-Speed CMOS Logic Triple 3-Input NOR Gate Type Features: • B uffered Inputs ■ Typical CD54/74HC27 P ropagation Delay = 7ns @ ^cc = 5v, Cl= 15pF, Ta = 25° C FUNCTIONAL DIAGRAM AND TERMINAL A SSIGNM ENT


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    PDF CD54/74HC27 CD54/74HCT27 CD54/74HC27 RCA-CD54/74HC27 CD54/74HCT27 CD54/74HCT 54LS/74LS D54HC27 CD54HCT27 14-lead

    T27b

    Abstract: No abstract text available
    Text: r z 7 S G S -T H O M S O N [j«M i[L i g im «S M 54HCT27 M 74HCT27 TRIPLE 3-INPUT NOR GATE • HIGHSPEED tpD = 9 ns (T Y P . A T V cc = 5 V . L O W P O W E R D IS S IP A T IO N Ice = 1 HA (M AX.) A T Ta = 2 5 C m C O M P A T IB L E W IT H T T L O U T P U T S


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    PDF 54HCT27 74HCT27 10LSTTL M54/74HCT27 T27b

    74HC27

    Abstract: No abstract text available
    Text: HARRIS SEMICOND SECTOR 27E D • 4302571 00174=15 0 ■¡HAS Technical D _ CD54/74HC27 CD54/74HCT27 File Number 1648 T~- 4 3 'X i- O O High-Speed CMOS Logic Triple 3-Input NOR Gate


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    PDF CD54/74HC27 CD54/74HCT27 RCA-CD54/74HC27 CD54/74HCT 74HCT 54HCT 54/74HC 54/74HCT 74HC27

    74hc273

    Abstract: 74HCT273
    Text: Technical Data CD54/74HC273 CD54/74HCT273 File Number 1 4 7 9 .1 High-Speed CMOS Logic Octal D Flip-Flop with Reset CLOCK CP “ D 2- -QO - 01 -02 03- -0 3 00□I - DATA _ IN P U T S 04- -0 4 05- -0 5 06- -0 6 07- -0 7 RESET TTR _ OATA O U TP U TS Type Feature*:


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    74HCT273

    Abstract: j131 54HCT273 74HCT 74SC273 J13-1 D FLIPFLOP PIN CONFIGURATION
    Text: ^ S u p e r Z e x in c . HCT/SC273 O '.ta i D F lip F lo p W it h C le a r »Preliminary Military 54HCT High Speed (74HCT) Standard (74SC) Octal D flip-flop with Clear 74HCT273 74SC273 54HCT273 Operating temperature range ( ° C) - 4 0 to + 8 5 - 4 0 to + 8 5


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    PDF HCT/SC273 74HCT) 54HCT) 74HCT273 74SC273 54HCT273 54/74LS 10/jA j131 54HCT273 74HCT J13-1 D FLIPFLOP PIN CONFIGURATION