AN-1059
Abstract: AN-1163 DS90C387 DS90CF384A DS90CF386 DS90CF388
Text: DS90C387/DS90CF388 Dual Pixel LVDS Display Interface LDI -SVGA/QXGA General Description Features The DS90C387/DS90CF388 transmitter/receiver pair is designed to support dual pixel data transmission between Host and Flat Panel Display up to QXGA resolutions. The transmitter converts 48 bits (Dual Pixel 24-bit color) of CMOS/TTL
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Original
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DS90C387/DS90CF388
DS90C387/DS90CF388
24-bit
112MHz,
672Mbps,
38Gbps
AN-1059
AN-1163
DS90C387
DS90CF384A
DS90CF386
DS90CF388
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PDF
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Untitled
Abstract: No abstract text available
Text: DS90CR483A, DS90CR484A www.ti.com SNLS291A – APRIL 2008 – REVISED APRIL 2013 DS90CR483A / DS90CR484A 48-Bit LVDS Channel Link SER/DES – 33 - 112 MHz Check for Samples: DS90CR483A, DS90CR484A FEATURES 1 • • • 2 • • • • • • • • •
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Original
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DS90CR483A,
DS90CR484A
SNLS291A
DS90CR483A
DS90CR484A
48-Bit
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PDF
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Untitled
Abstract: No abstract text available
Text: DS90CR481, DS90CR482 www.ti.com SNLS137D – NOVEMBER 2000 – REVISED APRIL 2013 DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz Check for Samples: DS90CR481, DS90CR482 FEATURES 1 • • • • 2 • • • • • • • • 3.168 Gbits/sec Bandwidth with 66 MHz Clock
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Original
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DS90CR481,
DS90CR482
SNLS137D
DS90CR481
DS90CR482
48-Bit
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PDF
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Untitled
Abstract: No abstract text available
Text: September 1999 DS90C387/DS90CF388 Dual Pixel LVDS Display Interface LDI -SVGA/QXGA General Description The DS90C387/DS90CF388 transmitter/receiver pair is designed to support dual pixel data transmission between Host and Flat Panel Display up to QXGA resolutions. The transmitter converts 48 bits (Dual Pixel 24-bit color) of CMOS/TTL
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Original
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DS90C387/DS90CF388
24-bit
112MHz,
672Mbps,
38Gbps
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PDF
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Untitled
Abstract: No abstract text available
Text: DS90CR483 / DS90CR484 48-Bit LVDS Channel Link Serializer/Deserializer General Description The DS90CR483 transmitter converts 48 bits of CMOS/TTL data into eight LVDS Low Voltage Differential Signaling data streams. A phase-locked transmit clock is transmitted in
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Original
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DS90CR483/DS90CR484
48-Bit
DS90CR483
DS90CR484
112MHz,
672Mbps
112MHz
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PDF
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Untitled
Abstract: No abstract text available
Text: DS90CR483A, DS90CR484A www.ti.com SNLS291A – APRIL 2008 – REVISED APRIL 2013 DS90CR483A / DS90CR484A 48-Bit LVDS Channel Link SER/DES – 33 - 112 MHz Check for Samples: DS90CR483A, DS90CR484A FEATURES 1 • • • 2 • • • • • • • • •
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Original
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DS90CR483A,
DS90CR484A
SNLS291A
DS90CR483A
DS90CR484A
48-Bit
ANSI/TIA/EIA-644-1995
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PDF
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lvds 40 pin pinout
Abstract: 100L DS90CR483 DS90CR483VJD DS90CR484 DS90CR484VJD VJD100A
Text: DS90CR483 / DS90CR484 48-Bit LVDS Channel Link SER/DES — 33 - 112 MHz General Description The DS90CR483 transmitter converts 48 bits of CMOS/TTL data into eight LVDS Low Voltage Differential Signaling data streams. A phase-locked transmit clock is transmitted in
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Original
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DS90CR483
DS90CR484
48-Bit
DS90CR484
112MHz,
672Mbps
112MHz
38Gbit/s
672Mbytes/s)
lvds 40 pin pinout
100L
DS90CR483VJD
DS90CR484VJD
VJD100A
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PDF
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Untitled
Abstract: No abstract text available
Text: DS90CR481, DS90CR482 www.ti.com SNLS137C – MAY 2004 – REVISED JANUARY 2006 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz Check for Samples: DS90CR481, DS90CR482 FEATURES 1 • • • • 2 • • 3.168 Gbits/sec bandwidth with 66 MHz Clock 5.376 Gbits/sec bandwidth with 112 MHz Clock
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Original
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DS90CR481,
DS90CR482
SNLS137C
48-Bit
ANSI/TIA/EIA-644-1995
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PDF
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FLM G12
Abstract: AN-1059 DS90C387 DS90CF388 "DUAL pixel" Programmable LVDS Receiver 24-Bit RGB
Text: July 2000 DS90C387/DS90CF388 Dual Pixel LVDS Display Interface LDI -SVGA/QXGA General Description The DS90C387/DS90CF388 transmitter/receiver pair is designed to support dual pixel data transmission between Host and Flat Panel Display up to QXGA resolutions. The transmitter converts 48 bits (Dual Pixel 24-bit color) of CMOS/TTL
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Original
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DS90C387/DS90CF388
DS90C387/DS90CF388
24-bit
112MHz,
672Mbps,
38Gbps
FLM G12
AN-1059
DS90C387
DS90CF388
"DUAL pixel"
Programmable LVDS Receiver 24-Bit RGB
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PDF
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DS90CR483VJD
Abstract: No abstract text available
Text: DS90CR483,DS90CR484 DS90CR483 / DS90CR484 48-Bit LVDS Channel Link SER/DES — 33 - 112 MHz Literature Number: SNLS047G DS90CR483 / DS90CR484 48-Bit LVDS Channel Link SER/DES — 33 - 112 MHz General Description The DS90CR483 transmitter converts 48 bits of CMOS/TTL
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Original
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DS90CR483
DS90CR484
DS90CR484
48-Bit
SNLS047G
DS90CR483/DS90CR484
DS90CR483VJD
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PDF
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LVDS 8BIT Tx. 2002 DIGITAL VIEW LTD
Abstract: No abstract text available
Text: DS90CR483 / DS90CR484 48-Bit LVDS Channel Link Serializer/Deserializer General Description The DS90CR483 transmitter converts 48 bits of CMOS/TTL data into eight LVDS Low Voltage Differential Signaling data streams. A phase-locked transmit clock is transmitted in
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Original
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DS90CR483/DS90CR484
48-Bit
DS90CR483
DS90CR484
112MHz,
672Mbps
112MHz
LVDS 8BIT Tx. 2002 DIGITAL VIEW LTD
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PDF
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AN-1163
Abstract: to112MHz
Text: November 2000 DS90C387/DS90CF388 Dual Pixel LVDS Display Interface LDI -SVGA/QXGA General Description Features The DS90C387/DS90CF388 transmitter/receiver pair is designed to support dual pixel data transmission between Host and Flat Panel Display up to QXGA resolutions. The transmitter converts 48 bits (Dual Pixel 24-bit color) of CMOS/TTL
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Original
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DS90C387/DS90CF388
24-bit
112MHz,
672Mbps,
38Gbps
14-Sep-
18-Feb-
5-Dec-2000]
AN-1163
to112MHz
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PDF
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marking G15
Abstract: No abstract text available
Text: July 2000 DS90C387/DS90CF388 Dual Pixel LVDS Display Interface LDI -SVGA/QXGA General Description The DS90C387/DS90CF388 transmitter/receiver pair is designed to support dual pixel data transmission between Host and Flat Panel Display up to QXGA resolutions. The transmitter converts 48 bits (Dual Pixel 24-bit color) of CMOS/TTL
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Original
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DS90C387/DS90CF388
24-bit
112MHz,
672Mbps,
38Gbps
AN-1163:
2-Sep-2000]
14-Sep-
marking G15
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PDF
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Untitled
Abstract: No abstract text available
Text: DS90C387, DS90CF388 www.ti.com SNLS012H – MAY 2000 – REVISED APRIL 2013 DS90C387, DS90CF388 Dual Pixel LVDS Display Interface LDI -SVGA/QXGA Check for Samples: DS90C387, DS90CF388 FEATURES DESCRIPTION • The DS90C387/DS90CF388 transmitter/receiver pair
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Original
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DS90C387,
DS90CF388
SNLS012H
DS90CF388
DS90C387/DS90CF388
24-bit
112MHz,
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PDF
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DS90CR483
Abstract: DS90CR484
Text: DS90CR483 / DS90CR484 48-Bit LVDS Channel Link Serializer/Deserializer General Description The DS90CR483 transmitter converts 48 bits of CMOS/TTL data into eight LVDS Low Voltage Differential Signaling data streams. A phase-locked transmit clock is transmitted in
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Original
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DS90CR483
DS90CR484
48-Bit
DS90CR484
112MHz,
672Mbps
112MHz
38Gbit/s
672Mbytes/s)
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PDF
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MDR 26 pin MINI D ribbon
Abstract: lvds 40 pin pinout pin connection lvds cable MDR 20 pin MINI D ribbon MDR 26 pin lvds connector 40 pin LVDS 30 pin connector cable cable tie LVDS connector 26 pin LVDS connector 40 pins
Text: DS90CR483A / DS90CR484A 48-Bit LVDS Channel Link SER/DES – 33 - 112 MHz General Description The DS90CR483A transmitter converts 48 bits of CMOS/TTL data into eight LVDS Low Voltage Differential Signaling data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a ninth LVDS link. Every cycle
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Original
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DS90CR483A
DS90CR484A
48-Bit
DS90CR484A
112MHz,
672Mbps
112MHz
38Gbit/s
672Mbytes/s)
MDR 26 pin MINI D ribbon
lvds 40 pin pinout
pin connection lvds cable
MDR 20 pin MINI D ribbon
MDR 26 pin
lvds connector 40 pin
LVDS 30 pin connector cable
cable tie
LVDS connector 26 pin
LVDS connector 40 pins
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PDF
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100L
Abstract: DS90CR483 DS90CR483VJD DS90CR484 DS90CR484VJD VJD100A
Text: DS90CR483 / DS90CR484 48-Bit LVDS Channel Link SER/DES — 33 - 112 MHz General Description The DS90CR483 transmitter converts 48 bits of CMOS/TTL data into eight LVDS Low Voltage Differential Signaling data streams. A phase-locked transmit clock is transmitted in
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Original
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DS90CR483
DS90CR484
48-Bit
DS90CR484
112MHz,
672Mbps
112MHz
38Gbit/s
672Mbytes/s)
100L
DS90CR483VJD
DS90CR484VJD
VJD100A
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PDF
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circuit diagram vga transmitter and receiver
Abstract: AN-1059 AN-1163 DS90C387 DS90CF384A DS90CF386 DS90CF388
Text: DS90C387/DS90CF388 Dual Pixel LVDS Display Interface LDI -SVGA/QXGA General Description The DS90C387/DS90CF388 transmitter/receiver pair is designed to support dual pixel data transmission between Host and Flat Panel Display up to QXGA resolutions. The transmitter converts 48 bits (Dual Pixel 24-bit color) of CMOS/TTL
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Original
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DS90C387/DS90CF388
DS90C387/DS90CF388
24-bit
112MHz,
672Mbps,
38Gbps
circuit diagram vga transmitter and receiver
AN-1059
AN-1163
DS90C387
DS90CF384A
DS90CF386
DS90CF388
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PDF
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AN-1059
Abstract: AN-1163 DS90C387 DS90CF384A DS90CF386 DS90CF388
Text: DS90C387/DS90CF388 Dual Pixel LVDS Display Interface LDI -SVGA/QXGA General Description The DS90C387/DS90CF388 transmitter/receiver pair is designed to support dual pixel data transmission between Host and Flat Panel Display up to QXGA resolutions. The transmitter converts 48 bits (Dual Pixel 24-bit color) of CMOS/TTL
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Original
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DS90C387/DS90CF388
DS90C387/DS90CF388
24-bit
112MHz,
672Mbps,
38Gbps
CSP-9-111S2)
CSP-9-111S2.
AN-1059
AN-1163
DS90C387
DS90CF384A
DS90CF386
DS90CF388
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PDF
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Untitled
Abstract: No abstract text available
Text: November 2000 DS90C387/DS90CF388 Dual Pixel LVDS Display Interface LDI -SVGA/QXGA General Description Features The DS90C387/DS90CF388 transmitter/receiver pair is designed to support dual pixel data transmission between Host and Flat Panel Display up to QXGA resolutions. The transmitter converts 48 bits (Dual Pixel 24-bit color) of CMOS/TTL
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Original
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DS90C387/DS90CF388
DS90C387/DS90CF388
24-bit
112MHz,
672Mbps,
38Gbps
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PDF
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lvds cable dc
Abstract: AN1108 100L DS90CR481 DS90CR481VJD DS90CR482 DS90CR482VS AN1059 ds90
Text: ご注意：この日本語データシートは参考資料として提供しており内容 が最新でない場合があります。製品のご検討およびご採用に際 しては、必ず最新の英文データシートをご確認ください。
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Original
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112MHz
112MHz
80MHz
DS90CR481
DS90CR482
672Mbps
38Gbit/sec
672MB/sec)
lvds cable dc
AN1108
100L
DS90CR481
DS90CR481VJD
DS90CR482
DS90CR482VS
AN1059
ds90
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PDF
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Untitled
Abstract: No abstract text available
Text: May 1999 DS90CR483 / DS90CR484 48-Bit LVDS Channel Link Serializer General Description The DS90CR483 transmitter converts 48 bits of CMOS/TTL data into eight LVDS Low Voltage Differential Signaling data streams. A phase-locked transmit clock is transmitted in
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Original
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DS90CR483/DS90CR484
48-Bit
DS90CR483
DS90CR484
112MHz,
672Mbps
112MHz
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PDF
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Untitled
Abstract: No abstract text available
Text: DS90CR483A,DS90CR484A DS90CR483A/DS90CR484A 48-Bit LVDS Channel Link SER/DES 33-112 MHz Literature Number: SNLS291 DS90CR483A / DS90CR484A 48-Bit LVDS Channel Link SER/DES – 33 - 112 MHz General Description The DS90CR483A transmitter converts 48 bits of CMOS/TTL
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Original
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DS90CR483A
DS90CR484A
DS90CR483A/DS90CR484A
48-Bit
SNLS291
DS90CR484A
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PDF
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FLM G12
Abstract: EL B17
Text: Semiconductor PRELIMINARY April 1999 DS90C387/DS90CF388 Dual Pixel LVDS Display Interface LDQ-SVGA/QXGA General Description The DS90C387/DS90CF388 transmitter/receiver pair is de signed to support dual pixel data transmission between Host and Flat Panel Display up to QXGA resolutions. The trans
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OCR Scan
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DS90C387/DS90CF388
24-bit
112MHz,
672Mbps,
38Gbps
FLM G12
EL B17
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PDF
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