A101
Abstract: CY7C1333F CY7C1333F-100AC
Text: CY7C1333F 2-Mbit 64K x 32 Flow-through SRAM with NoBL Architecture Functional Description[1] Features • Can support up to 117-MHz bus operations with zero wait states. Data is transferred on every clock. The CY7C1333F is a 3.3V, 64K x 32 Synchronous
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CY7C1333F
117-MHz
CY7C1333F
A101
CY7C1333F-100AC
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A101
Abstract: CY7C1333F CY7C1333F-100AC 20306
Text: CY7C1333F 2-Mbit 64K x 32 Flow-through SRAM with NoBL Architecture Functional Description[1] Features • Can support up to 117-MHz bus operations with zero wait states. Data is transferred on every clock. The CY7C1333F is a 3.3V, 64K x 32 Synchronous
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CY7C1333F
117-MHz
CY7C1333F
A101
CY7C1333F-100AC
20306
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20306
Abstract: No abstract text available
Text: CY7C1333F 2-Mbit 64K x 32 Flow-through SRAM with NoBL Architecture Functional Description[1] Features • Can support up to 117-MHz bus operations with zero wait states. Data is transferred on every clock. The CY7C1333F is a 3.3V, 64K x 32 Synchronous
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CY7C1333F
117-MHz
100-MHz
CY7C1333F
20306
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Untitled
Abstract: No abstract text available
Text: CY7C1333F 2-Mbit 64K x 32 Flow-through SRAM with NoBL Architecture Functional Description[1] Features • Can support up to 117-MHz bus operations with zero wait states. Data is transferred on every clock. The CY7C1333F is a 3.3V, 64K x 32 Synchronous
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CY7C1333F
117-MHz
100-MHz
CY7C1333F
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20306
Abstract: No abstract text available
Text: CY7C1333F 2-Mb 64K x 32 Flow-through SRAM with NoBL Architecture Functional Description[1] Features • Can support up to 117-MHz bus operations with zero wait states.Data is transferred on every clock. The CY7C1333F is a 3.3V, 64K x 32 Synchronous Flow-through Burst SRAM designed specifically to support
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CY7C1333F
117-MHz
100-MHz
CY7C1333F
20306
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Untitled
Abstract: No abstract text available
Text: CY7C1333H PRELIMINARY 2-Mbit 64K x 32 Flow-Through SRAM with NoBL Architecture Features • Low standby power Functional Description[1] • Can support up to 133-MHz bus operations with zero wait states. The CY7C1333H is a 3.3V, 64K x 32 Synchronous Flow-through Burst SRAM designed specifically to support
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CY7C1333H
133-MHz
CY7C1333H
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Switching regulator, Pin 5, Clock
Abstract: No abstract text available
Text: CY7C1333H PRELIMINARY 2-Mbit 64K x 32 Flow-Through SRAM with NoBL Architecture Features • Low standby power Functional Description[1] • Can support up to 133-MHz bus operations with zero wait states. The CY7C1333H is a 3.3V, 64K x 32 Synchronous Flow-through Burst SRAM designed specifically to support
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CY7C1333H
133-MHz
CY7C1333H
Switching regulator, Pin 5, Clock
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am9064
Abstract: cvp 45 Am90C644
Text: Am90C644 64K X 4 CMOS DUAL-ARRAY MEMORY ADVANCE INFORMATION 64K x 4 organization High-speed access: tpAC - 1 00 ns Write-per-Bit mask allows separatewrite controls for each of the four DRAM input bits On-chip video shifter with up to 100Megapixel/sec. bandwidth
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Am90C644
100Megapixel/sec.
144-bit
WF010
WF000372
am9064
cvp 45
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4264 dram
Abstract: No abstract text available
Text: MICRON T E C H N O L O G Y INC 55E D • blllS4'ì DDDSb?^ 153 ■ MRN PRELIMINARY W1T4C4264 883C 64K X 1 DRAM | W |! C R Q N MILITARY DRAM 64K X 1 DRAM FAST PAGE MODE AVAILABLE AS MILITARY SPECIFICATIONS PIN ASSIGNMENT Top View • MIL-STD-883, Class B
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W1T4C4264
MIL-STD-883,
16-Pin
150mW
256-cycle
MT4C4264
4264 dram
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Untitled
Abstract: No abstract text available
Text: MT4C1670/1 L 64K X 16 DRAM |U |IC =R O N 64K x 16 DRAM STATIC COLUMN MODE, LOW POWER, EXTENDED REFRESH FEATURES PIN ASSIGNMENT Top View • Industry standard x l6 pinouts, tim ing, functions and packages • High-perform ance, CM OS silicon-gate process
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MT4C1670/1
MT4C1670
MT4C1671
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Untitled
Abstract: No abstract text available
Text: ADAPTEC INC y •: MME D ■ B OElMMlb GQG203D & D A A C ¿ m $ L - i .j " .'T 'S L ^ k '5 Ç\C\ A IP -Æ 1 r 1 1O U I U U Single-Chip PC/AT Mass Storage Controller DATA BUFFER SRAM 64K MAX DRAM 64K MAX 8 MB/sec 3,5/2,5 INCH HARD DISK t AT BUS DATA SEPARATOR
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GQG203D
AIC-6160
16-byte
AIC-010
32-bit
48-bit
16-bit
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4264 dram
Abstract: No abstract text available
Text: AUSTI N S E M I C O N D U C T O R INC bOE D I D O E l l ? G G G G 1 1 4 7Ü4 H A U S T K K tL IM IN A K Y MT4C4264 883C 64K X 1 DRAM |U|IC=RON MILITARY DRAM 64K X 1 DRAM FAST PAGE MODE AVAILABLE AS MILITARY SPECIFICATIONS PIN ASSIGNMENT Top View • MIL-STD-883, Class B
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MT4C4264
MIL-STD-883,
16-Pin
150mW
256-cycle
4264 dram
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n6480
Abstract: 347I
Text: HIGH-SPEED 64K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS IDT707288S/L Features * * * * * 64K x 16 Bank-Switchable Dual-Ported SRAM Architecture - Four independent 16K x 16 banks * - 1 M egabit o f mem ory on chip * Fast asynchronous address-to-data access time: 15ns
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IDT707288S/L
16Kxl6
16-bit
100-pin
MO-136,
i-M74
S10-U9-2070
PSC-4036
n6480
347I
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Untitled
Abstract: No abstract text available
Text: HIGH-SPEED 64K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS IDT707288S/L F e a tu re s * * * * * 64K x 16 Bank-Switchable Dual-Ported SRAM Architecture - Four independent 16K x 16 banks * - 1 M egabit o f mem ory on chip * Fast asynchronous address-to-data access time: 15ns
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IDT707288S/L
16-bit
492-M
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3771 8 pin ic
Abstract: 3771 ic 8 pin 8 pin ic 3771 3771 1A7A1 3771- IC
Text: LOW POWER 3V CMOS SRAM 1 MEG 64K x 16-BIT ADVANCE INFORMATION IDT71V016L Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • • • • • • • The ID T71V016L is a 1,048,576-bit very low-pow er Static RAM organized as 64K x 16. It is fabricated using ID T’s highreliability CMOS technology. This state-of-the-art technology,
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16-BIT)
IDT71V016L
100ns
44-pin
576-bit
71V016
400-mil
3771 8 pin ic
3771 ic 8 pin
8 pin ic 3771
3771
1A7A1
3771- IC
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3771
Abstract: 3771 ic 8 pin
Text: LOW POWER 3V CMOS SRAM 1 MEG 64K x 16-BIT ADVANCE INFORMATION IDT71V016L Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • • • • • • • The ID T71V016L is a 1,048,576-bit very low-pow er Static RAM organized as 64K x 16. It is fabricated using ID T’s highreliability CMOS technology. This state-of-the-art technology,
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16-BIT)
IDT71V016L
100ns
44-pin
T71V016L
576-bit
9S054
3771
3771 ic 8 pin
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7481 memory ics
Abstract: oti-037
Text: OAK TECHNOLOGY INC. OTI-037 SYSTEM BLOCK DIAGRAM REFRESH SIR SIW SMR OTI-037 -RASO -CAS -W E -O E -IO W R -RAS -CAS -W E -O E BUS INTERFACE PLANEO 64K BYTE MD0-MD7 DATA ADDRESS I MDO-MD7 ASEL SA8-SA16 -RAS -CAS WE -O E PLANE 1 64K BYTE RAS -CAS -W E -O E PLANE 2
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OTI-037
SA8-SA16
MD8-MD15
SA0-SA19
MD16-MD23
MD24-MD31
7481 memory ics
oti-037
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58AZ
Abstract: No abstract text available
Text: Am29368 Advanced Micro Devices 1 Megabit Dynamic Memory Controller/Driver DMC DISTINCTIVE CHARACTERISTICS Provides control for 16K, 64K, and 256K and 1-megabit dynamic RAMs Outputs directly drive up to 88 DRAMs. with a guaran teed worst-case limit on the undershoot
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Am29368
Am2968A
32-bit
QP002600
58AZ
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78D015
Abstract: No abstract text available
Text: MT4C1670/1 64K X 16 DRAM | V | IC = R O N DRAM 64K x 16DRAM STATIC COLUMN MODE FEATURES PIN ASSIGNMENT Top View • Ind u stry sta n d a rd x l 6 p in o u ts, tim ing , fu n ctio n s and p ackages • • • • • • H ig h -p erfo rm an ce, C M O S silico n -g a te p ro cess
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MT4C1670/1
16DRAM
40-Pin
OE1992,
78D015
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AM29368
Abstract: CGX068
Text: Am29368 Advanced Micro Devices 1 Megabit Dynamic Memory Controller/Driver DMC DISTINCTIVE CHARACTERISTICS Provides control for 16K, 64K, and 256K and 1-megabit dynamic RAMs Outputs directly drive up to 8 8 DRAMs, with a guaran teed worst-case limit on the undershoot
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Am29368
Am2968A
32-bit
OP002600
CGX068
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6164 ram memory
Abstract: No abstract text available
Text: a Am29368 Advanced Micro Devices 1 Megabit Dynamic Memory Controller/Driver DMC DISTINCTIVE CHARACTERISTICS Provides control for 16K, 64K, and 256K and 1-megabit dynamic RAMs Outputs directly drive up to 8 8 DRAMs, with a guaran teed worst-case limit on the undershoot
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Am29368
Am2968A
32-bit
QP002600
6164 ram memory
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Untitled
Abstract: No abstract text available
Text: J MN1020019 / 0219 / 0419 / 0819 MN1020019 / 0219 / 0419 / 0819 1 Type 1 ROM x8-bit/x16-bit External / 1 6K / 32K / 64K (External Memory Expandable) 1 RAM (x8-bit/x16-bit) 3K / 1 K / 2K / 3K (External Memory Expandable) I Minimum Instruction Execution Time
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MN1020019
x8-bit/x16-bit)
100ns
20MHz)
200ns
10MHz)
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Untitled
Abstract: No abstract text available
Text: 8-Bit Dynamic-RAM Driver with Three-state Outputs SN54/74S700/-1 SN54/74S731/-1 SN54/74S730/-1 SN54/74S734/-1 Ordering Information Features/ Benefits: • Provides MOS voltage levels lo r 16K and 64K DRAMs PART NUMBER PKG TEMP ENABLE POLARITY POWER • Undershoot of low-going output is less than -0 .5 V
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SN54/74S700/-1
SN54/74S731/-1
SN54/74S730/-1
SN54/74S734/-1
SN54S700/-1
SN74S700/-1
SN54S730/-1
20-pin
S730/734
Am2965/66
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Untitled
Abstract: No abstract text available
Text: LOW POWER 2V CMOS SRAM 1 MEG 64K x 16-BIT ADVANCE INFORMATION IDT71T016 I n te g r a te d D e v iz e T e c h n o lo g y , l i e . FEATURES: DESCRIPTION: • 64K x 16 Organization • Wide Operating Voltage Range: 1.8 to 2.7V • Commercial (0° to 70°C) and Industrial (-40° to 85°C)
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16-BIT)
IDT71T016
150ns,
200ns
10jxA
44-pin
46-BALL
IDT71T016
576-bit
10-338-207Q
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