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    2KX18 Search Results

    2KX18 Result Highlights (1)

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    CY7C457-12NC-G Rochester Electronics LLC CY7C457 - FIFO, 2KX18, Synchronous Visit Rochester Electronics LLC Buy
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    2KX18 Price and Stock

    Murata Manufacturing Co Ltd BLM02KX180SN1D

    FERRITE BEAD 18 OHM 01005 1LN
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    DigiKey BLM02KX180SN1D Cut Tape 34,965 1
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    BLM02KX180SN1D Digi-Reel 34,965 1
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    BLM02KX180SN1D Reel 30,000 15,000
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    Avnet Americas BLM02KX180SN1D Reel 12 Weeks 15,000
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    Mouser Electronics BLM02KX180SN1D 2,550
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    Newark BLM02KX180SN1D Cut Tape 11,378 10
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    TME BLM02KX180SN1D 15,000
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    Avnet Abacus BLM02KX180SN1D 11 Weeks 15,000
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    Novacap RC4040R164K142KX180T

    MULTILAYER CERAMIC CAPACITOR
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    DigiKey RC4040R164K142KX180T Bulk 250
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    TDK Corporation B66482KX187

    Planar Core Inductor 3400nH N87 100kHz - Trays (Alt: B66482K0000X187)
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    Avnet Americas B66482KX187 Tray 18 Weeks 1,080
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    Knowles Corporation RC4040R164K142KX180T

    Multilayer Ceramic Capacitors MLCC - SMD/SMT Multilayer Ceramic Capacitor
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    Mouser Electronics RC4040R164K142KX180T
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    Tecate Group CMC-2K0/152KX1812T13

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    Bristol Electronics CMC-2K0/152KX1812T13 2,000
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    2KX18 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    C4558

    Abstract: C4554 C4557 c455 CY7C455-14JI CY7C455 CY7C456 CY7C457 CY7C447
    Text: CY7C455 CY7C456 CY7C457 512 x 18, 1K x 18, and 2K x 18 Cascadable Clocked FIFOs with Programmable Flags • Depth Expansion Capability • 52-pin PLCC and 52-pin PQFP Features • High-speed, low-power, first-in first-out FIFO memories • 512 x 18 (CY7C455)


    Original     		PDF CY7C455 CY7C456 CY7C457 52-pin CY7C455) CY7C456) CY7C457) 83-MHz C4558 C4554 C4557 c455 CY7C455-14JI CY7C455 CY7C456 CY7C457 CY7C447

    723653

    Abstract: 72V7290 72V3613 72V7250 72V3611 72V3623 72V72100 72V7230 72V7240 72V7260
    Text: Selector Guide for FIFO Memory Products • Synchronous FIFOs SuperSync II, SuperSync™ SyncFIFO™, DualSync™ • Bi-Directional Synchronous FIFOs • Asynchronous FIFOs the leading provider of FIFO memories. July’00 IDT FIFO Memory Products Quick Reference Guide


    Original     		PDF 512-bit 16K-bit 64K-bit 128K-bit 256K-bit 512K-bit 100MHz 133MHz 723653 72V7290 72V3613 72V7250 72V3611 72V3623 72V72100 72V7230 72V7240 72V7260

    723653

    Abstract: BI 7284 72V7250 72V72100 72V7230 72V7240 72V7260 72V7270 72V7280 72V7290
    Text: Selector Guide for FIFO Memory Products • Synchronous FIFOs SuperSync II, SuperSync™ SyncFIFO™, DualSync™ • Bi-Directional Synchronous FIFOs • Asynchronous FIFOs the leading provider of FIFO memories. Jan’00 IDT FIFO Memory Products Quick Reference Guide


    Original     		PDF 512-bit 16K-bit 64K-bit 128K-bit 512K-bit 7236x3/72V36x3 723653 BI 7284 72V7250 72V72100 72V7230 72V7240 72V7260 72V7270 72V7280 72V7290

    KTA 3-25

    Abstract: verilog code for 8254 timer MCF5204 so-8 marking code cyle
    Text: ColdFire 2/2M Integrated Microprocessor User’s Manual Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and


    Original     		PDF

    Untitled

    Abstract: No abstract text available
    Text: 2.5 VOLT HIGH-SPEED TeraSync FIFO IDT72T1845, IDT72T1855 18-BIT/9-BIT CONFIGURATIONS IDT72T1865, IDT72T1875 2,048 x 18/4,096 x 9, 4,096 x 18/8,192 x 9, 8,192 x 18/16,384 x 9, IDT72T1885, IDT72T1895 16,384 x 18/32,768 x 9, 32,768 x 18/65,536 x 9, 65,536 x 18/131,072 x 9,


    Original     		PDF IDT72T1845, IDT72T1855 18-BIT/9-BIT IDT72T1865, IDT72T1875 IDT72T1885, IDT72T1895 IDT72T18105, IDT72T18115 IDT72T18125

    verilog code for dual port ram with axi interface

    Abstract: XC6SLX25T-2CSG324 UG473 verilog code for dual port ram with axi lite interface XC6VLX75T-2FF784 hamming code in vhdl axi wrapper blk_mem_gen verilog code for pseudo random sequence generator in state diagram of AMBA AXI protocol v 1.0
    Text: LogiCORE IP Block Memory Generator v7.1 DS512 April 24, 2012 Product Specification Introduction LogiCORE IP Facts The Xilinx LogiCORE IP Block Memory Generator BMG core is an advanced memory constructor that generates area and performance-optimized memories


    Original     		PDF DS512 verilog code for dual port ram with axi interface XC6SLX25T-2CSG324 UG473 verilog code for dual port ram with axi lite interface XC6VLX75T-2FF784 hamming code in vhdl axi wrapper blk_mem_gen verilog code for pseudo random sequence generator in state diagram of AMBA AXI protocol v 1.0

    IDT72T18105

    Abstract: IDT72T18115 IDT72T18125 IDT72T1845 IDT72T1855 IDT72T1865 IDT72T1875 IDT72T1885 IDT72T1895
    Text: 2.5 VOLT HIGH-SPEED TeraSync FIFO IDT72T1845, IDT72T1855 18-BIT/9-BIT CONFIGURATIONS IDT72T1865, IDT72T1875 2,048 x 18/4,096 x 9, 4,096 x 18/8,192 x 9, 8,192 x 18/16,384 x 9, IDT72T1885, IDT72T1895 16,384 x 18/32,768 x 9, 32,768 x 18/65,536 x 9, 65,536 x 18/131,072 x 9,


    Original     		PDF IDT72T1845, IDT72T1855 18-BIT/9-BIT IDT72T1865, IDT72T1875 IDT72T1885, IDT72T1895 IDT72T18105, IDT72T18115 IDT72T18125 IDT72T18105 IDT72T18115 IDT72T18125 IDT72T1845 IDT72T1855 IDT72T1865 IDT72T1875 IDT72T1885 IDT72T1895

    C4558

    Abstract: c455 CY7C455 CY7C456 CY7C457 CY7C447
    Text: 57 CY7C455 CY7C456 CY7C457 512 x 18, 1K x 18, and 2K x 18 Cascadable Clocked FIFOs with Programmable Flags Features • Depth Expansion Capability • 52-pin PLCC and 52-pin PQFP • High-speed, low-power, first-in first-out FIFO memories • 512 x 18 (CY7C455)


    Original     		PDF CY7C455 CY7C456 CY7C457 52-pin CY7C455) CY7C456) CY7C457) 83-MHz C4558 c455 CY7C455 CY7C456 CY7C457 CY7C447

    CY7C4271-JC

    Abstract: cypress 98267 9832 CY5037
    Text: CYPRESS SEMICONDUCTOR CORPORATION PRODUCT RELIABILITY REPORT QUARTER 4, 1998 PERFORM PER THE REQUIREMENT OF 25-00008, RELIABILITY MONITOR PROGRAM SPECIFICATION Ed Russell Reliability Manager CYPRESS SEMICONDUCTOR CORPORATION PRODUCT RELIABILITY REPORT Quarter 4, 1998


    Original     		PDF CY62128V-VC CY62128V-ZSC CY7C4271-JC cypress 98267 9832 CY5037

    32kx18

    Abstract: No abstract text available
    Text: 2.5 VOLT HIGH-SPEED TeraSync FIFO PRELIMINARY IDT72T1845, IDT72T1855 18-BIT/9-BIT CONFIGURATIONS IDT72T1865, IDT72T1875 2,048 x 18/4,096 x 9, 4,096 x 18/8,192 x 9, 8,192 x 18/16,384 x 9, IDT72T1885, IDT72T1895 16,384 x 18/32,768 x 9, 32,768 x 18/65,536 x 9, 65,536 x 18/131,072 x 9,


    Original     		PDF IDT72T1845, IDT72T1855 18-BIT/9-BIT IDT72T1865, IDT72T1875 IDT72T1885, IDT72T1895 IDT72T18105, IDT72T18115 IDT72T18125 32kx18

    A101L

    Abstract: No abstract text available
    Text: HIGH-SPEED 3.3V 128K x 18 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE PRELIMINARY IDT70V7399S Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ 128K x 18 Synchronous Bank-Switchable Dual-ported SRAM Architecture – 64 independent 2K x 18 banks


    Original     		PDF IDT70V7399S 166MHz 133MHz) 12Gbps A101L

    schematic diagram atx Power supply 500w

    Abstract: pioneer PAL 012A 1000w inverter PURE SINE WAVE schematic diagram 600va numeric ups circuit diagrams winbond bios 25064 TLE 9180 infineon smsc MEC 1300 nu TBE schematic diagram inverter 2000w DK55 circuit diagram of luminous 600va UPS
    Text: QUICK INDEX NEW IN THIS ISSUE! Detailed Index - See Pages 3-24 Digital Signal Processors, iCoupler , iMEMS® and iSensor . . . . . 805, 2707, 2768-2769 Connectors, Cable Assemblies, IC Sockets . . . . . . . . . . . 28-568 RF Connectors . . . . . . . . . . . . . . . . . . . . . . Pages 454-455


    Original     		PDF P462-ND P463-ND LNG295LFCP2U LNG395MFTP5U US2011) schematic diagram atx Power supply 500w pioneer PAL 012A 1000w inverter PURE SINE WAVE schematic diagram 600va numeric ups circuit diagrams winbond bios 25064 TLE 9180 infineon smsc MEC 1300 nu TBE schematic diagram inverter 2000w DK55 circuit diagram of luminous 600va UPS

    C4558

    Abstract: C4557 c4552 C4555 c4556 C-4555 c4554 c455 CY7C455 CY7C457
    Text: 57 CY7C455 CY7C456 CY7C457 512 x 18, 1K x 18, and 2K x 18 Cascadable Clocked FIFOs with Programmable Flags Features • Depth Expansion Capability • 52-pin PLCC and 52-pin PQFP • High-speed, low-power, first-in first-out FIFO memories • 512 x 18 (CY7C455)


    Original     		PDF CY7C455 CY7C456 CY7C457 52-pin CY7C455) CY7C456) CY7C457) 83-MHz C4558 C4557 c4552 C4555 c4556 C-4555 c4554 c455 CY7C455 CY7C457

    723653

    Abstract: 72V841 72825 72V3622 BI 7284 72V3613 723674 72V211 72V221 72V241
    Text: Selector Guide for FIFO Memory Products • Synchronous FIFOs SuperSync II, SuperSync™ SyncFIFO™, DualSync™ • Bi-Directional Synchronous FIFOs • Asynchronous FIFOs the leading provider of FIFO memories. July’99/PC IDT FIFO Memory Products Width


    Original     		PDF 99/PC 28-TP 36-bit 18-bit 723653 72V841 72825 72V3622 BI 7284 72V3613 723674 72V211 72V221 72V241

    M7401

    Abstract: m74010 m7402 M74050 M74040 M74064 m80129 hyundai 9750 9745-1 VIC068A cy7c199zi
    Text: CYPRESS SEMICONDUCTOR CORPORATION PRODUCT RELIABILITY REPORT QUARTER 1, 1998 PERFORM PER THE REQUIREMENT OF 25-00008, RELIABILITY MONITOR PROGRAM SPECIFICATION Marc Hartranft Reliability Manager CYPRESS SEMICONDUCTOR CORPORATION PRODUCT RELIABILITY REPORT


    Original     		PDF CY7C1334-AC M7401 m74010 m7402 M74050 M74040 M74064 m80129 hyundai 9750 9745-1 VIC068A cy7c199zi

    x-ray cmos

    Abstract: HX6409 6409D 6218 FIFO 065um capacitor enw
    Text: FIFO – HX6409/HX6218/HX6136 First-In First-Out Memory HX6409/HX6218/HX6136 The HX6409, HX6218, and HX6136 are high speed, low power, first-in first-out memories with clocked read and write interfaces. The HX6409 is a 4096-word by 9bit memory array; the HX6218 is a 2048-word by 18-bit


    Original     		PDF HX6409/HX6218/HX6136 HX6409, HX6218, HX6136 HX6409 4096-word HX6218 2048-word 18-bit x-ray cmos 6409D 6218 FIFO 065um capacitor enw

    CY62256LL-PC

    Abstract: VIC068A-GC VIC64-NC VIC64-UMB PALCE22V10-JI PALC16L8Q PLD VME A113 CY7B923 JESD22-A113
    Text: Cypress Semiconductor Product Reliability 1997 Published June, 1997 CYPRESS SEMICONDUCTOR PRODUCT RELIABILITY TABLE OF CONTENTS 1.0 OVERVIEW OF CYPRESS SEMICONDUCTOR TOTAL QUALITY MANAGEMENT SYSTEM. 1 2.0 ELECTRICAL AVERAGE OUTGOING QUALITY. 2


    Original     		PDF PALCE22V10-JC FLASH-FL22D CY62256LL-PC VIC068A-GC VIC64-NC VIC64-UMB PALCE22V10-JI PALC16L8Q PLD VME A113 CY7B923 JESD22-A113

    C4558

    Abstract: C4557 c4554 c455 CY7C455 CY7C456 CY7C457 c4556 C4559 CY7C447
    Text: fax id: 5408 1CY 7C45 7 CY7C455 CY7C456 CY7C457 512 x 18, 1K x 18, and 2K x 18 Cascadable Clocked FIFOs with Programmable Flags Features Functional Description • High-speed, low-power, first-in first-out FIFO memories • 512 x 18 (CY7C455) • 1,024 x 18 (CY7C456)


    Original     		PDF CY7C455 CY7C456 CY7C457 CY7C455) CY7C456) CY7C457) 83-MHz C4558 C4557 c4554 c455 CY7C455 CY7C456 CY7C457 c4556 C4559 CY7C447

    065um

    Abstract: No abstract text available
    Text: FIFO – HX6409/HX6218/HX6136 First-In First-Out Memory HX6409/HX6218/HX6136 The HX6409, HX6218, and HX6136 are high speed, low power, first-in first-out memories with clocked read and write interfaces. The HX6409 is a 4096-word by 9bit memory array; the HX6218 is a 2048-word by 18-bit


    Original     		PDF HX6409/HX6218/HX6136 HX6409, HX6218, HX6136 HX6409 4096-word HX6218 2048-word 18-bit 065um

    BGA 144

    Abstract: 208 BGA 72T3665 240-BGA 72T36125
    Text: Selector Guide for TeraSync FIFOs from the leading provider of FIFO solutions • 2.5V core voltage • 225 MHz high-speed operation • Densities up to 9 M-bit • 9, 18, 36, 72-bit configurations • BGA packaging, including JTAG TeraSync the next generation


    Original     		PDF 72-bit 16Kx72 32Kx72 64Kx72 128Kx72 72T7285 72T7295 72T72105 72T72115 72T3645 BGA 144 208 BGA 72T3665 240-BGA 72T36125

    XC6SL

    Abstract: SPARTAN 6 Configuration SPARTAN-6 DS512 RAMB36 RAMB18 RAMB18SDP hamming decoder vhdl code spartan 3 multiprocessor 2Kx18
    Text: Block Memory Generator v3.3 DS512 September 16, 2009 Product Specification Introduction • The Xilinx LogiCORE IP Block Memory Generator core is an advanced memory constructor that generates area and performance-optimized memories using embedded block RAM resources in Xilinx FPGAs.


    Original     		PDF DS512 XC6SL SPARTAN 6 Configuration SPARTAN-6 RAMB36 RAMB18 RAMB18SDP hamming decoder vhdl code spartan 3 multiprocessor 2Kx18

    5630 LED

    Abstract: LED 5630 5630 95A 640 ba6l 70V7399 IDT70V7399 IDT70V7399S BA6R IP LED 5630 G2
    Text: HIGH-SPEED 3.3V 128K x 18 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE IDT70V7399S Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ 128K x 18 Synchronous Bank-Switchable Dual-ported SRAM Architecture – 64 independent 2K x 18 banks – 2 megabits of memory on chip


    Original     		PDF IDT70V7399S 200MHz 166MHz 133MHz) 14Gbps SMEN-01-05 5630 LED LED 5630 5630 95A 640 ba6l 70V7399 IDT70V7399 IDT70V7399S BA6R IP LED 5630 G2

    LED 5630

    Abstract: 5630 LED 5630 70V7399 IDT70V7399 IDT70V7399S A101L
    Text: HIGH-SPEED 3.3V 128K x 18 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ 128K x 18 Synchronous Bank-Switchable Dual-ported SRAM Architecture – 64 independent 2K x 18 banks – 2 megabits of memory on chip


    Original     		PDF 200MHz 166MHz 133MHz) 14Gbps BC-256 LED 5630 5630 LED 5630 70V7399 IDT70V7399 IDT70V7399S A101L

    Untitled

    Abstract: No abstract text available
    Text: fax id: 5408 CY7C455 CY7C456 _ 0 CYPHjhoh 512 x 18, 1K x 18, and 2K x 18 Cascadable Clocked FIFOs with Programmable Flags Features Functional Description • High-speed, low-power, first-in first-out FIFO memories • 512 x 18 (CY7C455) • 1,024 x 18 (CY7C456)


    OCR Scan     		PDF CY7C455 CY7C456 CY7C455) CY7C456) CY7C457) 83-MHz